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imp-ID to 1

This commit is contained in:
waleed-lm 2020-12-17 17:25:17 +05:00
parent 158e702716
commit f36c650bf3
99 changed files with 18528 additions and 11092 deletions
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2
quasar_wrapper.anno.json
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@ -982,7 +982,7 @@
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|csr_tlu>_T_755"
"target":"~quasar_wrapper|csr_tlu>_T_745"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",

18164
quasar_wrapper.fir
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File diff suppressed because it is too large Load Diff

10428
quasar_wrapper.v
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File diff suppressed because it is too large Load Diff

6
src/main/scala/dec/dec.scala
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@ -245,10 +245,6 @@ class dec extends Module with param with RequireAsyncReset{
tlu.io.dbg_resume_req := io.dbg_resume_req
tlu.io.lsu_idle_any := io.lsu_idle_any
tlu.io.dec_div_active := decode.io.dec_div_active
// tlu.io.pic_claimid := io.dec_pic.pic_claimid
// tlu.io.pic_pl := io.dec_pic.pic_pl
// tlu.io.mhwakeup := io.dec_pic.mhwakeup
// tlu.io.mexintpend := io.mexintpend
tlu.io.timer_int := io.timer_int
tlu.io.soft_int := io.soft_int
tlu.io.core_id := io.core_id
@ -269,8 +265,6 @@ class dec extends Module with param with RequireAsyncReset{
io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
io.debug_brkpt_status := tlu.io.debug_brkpt_status
// io.dec_pic.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl
// io.dec_pic.dec_tlu_meipt := tlu.io.dec_tlu_meipt
io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1

448
src/main/scala/dec/dec_tlu_ctl.scala
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@ -154,105 +154,105 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val io = IO(new dec_tlu_ctl_IO)
val mtdata1_t = Wire(Vec(4,UInt(10.W)))
val pause_expired_wb =WireInit(UInt(1.W), 0.U)
val take_nmi_r_d1 =WireInit(UInt(1.W),0.U)
val exc_or_int_valid_r_d1 =WireInit(UInt(1.W),0.U)
val interrupt_valid_r_d1 =WireInit(UInt(1.W),0.U)
val tlu_flush_lower_r =WireInit(UInt(1.W),0.U)
val synchronous_flush_r =WireInit(UInt(1.W),0.U)
val interrupt_valid_r =WireInit(UInt(1.W),0.U)
val take_nmi =WireInit(UInt(1.W),0.U)
val take_reset =WireInit(UInt(1.W),0.U)
val take_int_timer1_int =WireInit(UInt(1.W),0.U)
val take_int_timer0_int =WireInit(UInt(1.W),0.U)
val take_timer_int =WireInit(UInt(1.W),0.U)
val take_soft_int =WireInit(UInt(1.W),0.U)
val take_ce_int =WireInit(UInt(1.W),0.U)
val take_ext_int_start =WireInit(UInt(1.W),0.U)
val ext_int_freeze =WireInit(UInt(1.W),0.U)
val ext_int_freeze_d1 =WireInit(UInt(1.W),0.U)
val take_ext_int_start_d1 =WireInit(UInt(1.W),0.U)
val take_ext_int_start_d2 =WireInit(UInt(1.W),0.U)
val take_ext_int_start_d3 =WireInit(UInt(1.W),0.U)
val fast_int_meicpct =WireInit(UInt(1.W),0.U)
val ignore_ext_int_due_to_lsu_stall =WireInit(UInt(1.W),0.U)
val take_ext_int =WireInit(UInt(1.W),0.U)
val internal_dbg_halt_timers =WireInit(UInt(1.W),0.U)
val int_timer1_int_hold =WireInit(UInt(1.W),0.U)
val int_timer0_int_hold =WireInit(UInt(1.W),0.U)
val mhwakeup_ready =WireInit(UInt(1.W),0.U)
val ext_int_ready =WireInit(UInt(1.W),0.U)
val ce_int_ready =WireInit(UInt(1.W),0.U)
val soft_int_ready =WireInit(UInt(1.W),0.U)
val timer_int_ready =WireInit(UInt(1.W),0.U)
val ebreak_to_debug_mode_r_d1 =WireInit(UInt(1.W),0.U)
val ebreak_to_debug_mode_r =WireInit(UInt(1.W),0.U)
val inst_acc_r =WireInit(UInt(1.W),0.U)
val inst_acc_r_raw =WireInit(UInt(1.W),0.U)
val iccm_sbecc_r =WireInit(UInt(1.W),0.U)
val ic_perr_r =WireInit(UInt(1.W),0.U)
val fence_i_r =WireInit(UInt(1.W),0.U)
val ebreak_r =WireInit(UInt(1.W),0.U)
val ecall_r =WireInit(UInt(1.W),0.U)
val illegal_r =WireInit(UInt(1.W),0.U)
val mret_r =WireInit(UInt(1.W),0.U)
val iccm_repair_state_ns =WireInit(UInt(1.W),0.U)
val rfpc_i0_r =WireInit(UInt(1.W),0.U)
val tlu_i0_kill_writeb_r =WireInit(UInt(1.W),0.U)
val lsu_exc_valid_r_d1 =WireInit(UInt(1.W),0.U)
val lsu_i0_exc_r_raw =WireInit(UInt(1.W),0.U)
val mdseac_locked_f =WireInit(UInt(1.W),0.U)
val i_cpu_run_req_d1 =WireInit(UInt(1.W),0.U)
val cpu_run_ack =WireInit(UInt(1.W),0.U)
val cpu_halt_status =WireInit(UInt(1.W),0.U)
val cpu_halt_ack =WireInit(UInt(1.W),0.U)
val pmu_fw_tlu_halted =WireInit(UInt(1.W),0.U)
val internal_pmu_fw_halt_mode =WireInit(UInt(1.W),0.U)
val pmu_fw_halt_req_ns =WireInit(UInt(1.W),0.U)
val pmu_fw_halt_req_f =WireInit(UInt(1.W),0.U)
val pmu_fw_tlu_halted_f =WireInit(UInt(1.W),0.U)
val int_timer0_int_hold_f =WireInit(UInt(1.W),0.U)
val int_timer1_int_hold_f =WireInit(UInt(1.W),0.U)
val trigger_hit_dmode_r =WireInit(UInt(1.W),0.U)
val i0_trigger_hit_r =WireInit(UInt(1.W),0.U)
val pause_expired_r =WireInit(UInt(1.W),0.U)
val dec_tlu_pmu_fw_halted =WireInit(UInt(1.W),0.U)
val dec_tlu_flush_noredir_r_d1 =WireInit(UInt(1.W),0.U)
val halt_taken_f =WireInit(UInt(1.W),0.U)
val lsu_idle_any_f =WireInit(UInt(1.W),0.U)
val ifu_miss_state_idle_f =WireInit(UInt(1.W),0.U)
val dbg_tlu_halted_f =WireInit(UInt(1.W),0.U)
val debug_halt_req_f =WireInit(UInt(1.W),0.U)
val debug_resume_req_f =WireInit(UInt(1.W),0.U)
val trigger_hit_dmode_r_d1 =WireInit(UInt(1.W),0.U)
val dcsr_single_step_done_f =WireInit(UInt(1.W),0.U)
val debug_halt_req_d1 =WireInit(UInt(1.W),0.U)
val request_debug_mode_r_d1 =WireInit(UInt(1.W),0.U)
val request_debug_mode_done_f =WireInit(UInt(1.W),0.U)
val dcsr_single_step_running_f =WireInit(UInt(1.W),0.U)
val dec_tlu_flush_pause_r_d1 =WireInit(UInt(1.W),0.U)
val dbg_halt_req_held =WireInit(UInt(1.W),0.U)
val debug_halt_req_ns =WireInit(UInt(1.W),0.U)
val internal_dbg_halt_mode =WireInit(UInt(1.W),0.U)
val core_empty =WireInit(UInt(1.W),0.U)
val dbg_halt_req_final =WireInit(UInt(1.W),0.U)
val debug_brkpt_status_ns =WireInit(UInt(1.W),0.U)
val mpc_debug_halt_ack_ns =WireInit(UInt(1.W),0.U)
val mpc_debug_run_ack_ns =WireInit(UInt(1.W),0.U)
val mpc_halt_state_ns =WireInit(UInt(1.W),0.U)
val mpc_run_state_ns =WireInit(UInt(1.W),0.U)
val dbg_halt_state_ns =WireInit(UInt(1.W),0.U)
val dbg_run_state_ns =WireInit(UInt(1.W),0.U)
val dbg_halt_state_f =WireInit(UInt(1.W),0.U)
val mpc_halt_state_f =WireInit(UInt(1.W),0.U)
val nmi_int_detected =WireInit(UInt(1.W),0.U)
val nmi_lsu_load_type =WireInit(UInt(1.W),0.U)
val nmi_lsu_store_type =WireInit(UInt(1.W),0.U)
val reset_delayed =WireInit(UInt(1.W),0.U)
val internal_dbg_halt_mode_f =WireInit(UInt(1.W),0.U)
val e5_valid =WireInit(UInt(1.W),0.U)
val ic_perr_r_d1 =WireInit(UInt(1.W),0.U)
val iccm_sbecc_r_d1 =WireInit(UInt(1.W),0.U)
val pause_expired_wb = WireInit(UInt(1.W), 0.U)
val take_nmi_r_d1 = WireInit(UInt(1.W),0.U)
val exc_or_int_valid_r_d1 = WireInit(UInt(1.W),0.U)
val interrupt_valid_r_d1 = WireInit(UInt(1.W),0.U)
val tlu_flush_lower_r = WireInit(UInt(1.W),0.U)
val synchronous_flush_r = WireInit(UInt(1.W),0.U)
val interrupt_valid_r = WireInit(UInt(1.W),0.U)
val take_nmi = WireInit(UInt(1.W),0.U)
val take_reset = WireInit(UInt(1.W),0.U)
val take_int_timer1_int = WireInit(UInt(1.W),0.U)
val take_int_timer0_int = WireInit(UInt(1.W),0.U)
val take_timer_int = WireInit(UInt(1.W),0.U)
val take_soft_int = WireInit(UInt(1.W),0.U)
val take_ce_int = WireInit(UInt(1.W),0.U)
val take_ext_int_start = WireInit(UInt(1.W),0.U)
val ext_int_freeze = WireInit(UInt(1.W),0.U)
val ext_int_freeze_d1 = WireInit(UInt(1.W),0.U)
val take_ext_int_start_d1 = WireInit(UInt(1.W),0.U)
val take_ext_int_start_d2 = WireInit(UInt(1.W),0.U)
val take_ext_int_start_d3 = WireInit(UInt(1.W),0.U)
val fast_int_meicpct = WireInit(UInt(1.W),0.U)
val ignore_ext_int_due_to_lsu_stall = WireInit(UInt(1.W),0.U)
val take_ext_int = WireInit(UInt(1.W),0.U)
val internal_dbg_halt_timers = WireInit(UInt(1.W),0.U)
val int_timer1_int_hold = WireInit(UInt(1.W),0.U)
val int_timer0_int_hold = WireInit(UInt(1.W),0.U)
val mhwakeup_ready = WireInit(UInt(1.W),0.U)
val ext_int_ready = WireInit(UInt(1.W),0.U)
val ce_int_ready = WireInit(UInt(1.W),0.U)
val soft_int_ready = WireInit(UInt(1.W),0.U)
val timer_int_ready = WireInit(UInt(1.W),0.U)
val ebreak_to_debug_mode_r_d1 = WireInit(UInt(1.W),0.U)
val ebreak_to_debug_mode_r = WireInit(UInt(1.W),0.U)
val inst_acc_r = WireInit(UInt(1.W),0.U)
val inst_acc_r_raw = WireInit(UInt(1.W),0.U)
val iccm_sbecc_r = WireInit(UInt(1.W),0.U)
val ic_perr_r = WireInit(UInt(1.W),0.U)
val fence_i_r = WireInit(UInt(1.W),0.U)
val ebreak_r = WireInit(UInt(1.W),0.U)
val ecall_r = WireInit(UInt(1.W),0.U)
val illegal_r = WireInit(UInt(1.W),0.U)
val mret_r = WireInit(UInt(1.W),0.U)
val iccm_repair_state_ns = WireInit(UInt(1.W),0.U)
val rfpc_i0_r = WireInit(UInt(1.W),0.U)
val tlu_i0_kill_writeb_r = WireInit(UInt(1.W),0.U)
val lsu_exc_valid_r_d1 = WireInit(UInt(1.W),0.U)
val lsu_i0_exc_r_raw = WireInit(UInt(1.W),0.U)
val mdseac_locked_f = WireInit(UInt(1.W),0.U)
val i_cpu_run_req_d1 = WireInit(UInt(1.W),0.U)
val cpu_run_ack = WireInit(UInt(1.W),0.U)
val cpu_halt_status = WireInit(UInt(1.W),0.U)
val cpu_halt_ack = WireInit(UInt(1.W),0.U)
val pmu_fw_tlu_halted = WireInit(UInt(1.W),0.U)
val internal_pmu_fw_halt_mode = WireInit(UInt(1.W),0.U)
val pmu_fw_halt_req_ns = WireInit(UInt(1.W),0.U)
val pmu_fw_halt_req_f = WireInit(UInt(1.W),0.U)
val pmu_fw_tlu_halted_f = WireInit(UInt(1.W),0.U)
val int_timer0_int_hold_f = WireInit(UInt(1.W),0.U)
val int_timer1_int_hold_f = WireInit(UInt(1.W),0.U)
val trigger_hit_dmode_r = WireInit(UInt(1.W),0.U)
val i0_trigger_hit_r = WireInit(UInt(1.W),0.U)
val pause_expired_r = WireInit(UInt(1.W),0.U)
val dec_tlu_pmu_fw_halted = WireInit(UInt(1.W),0.U)
val dec_tlu_flush_noredir_r_d1= WireInit(UInt(1.W),0.U)
val halt_taken_f = WireInit(UInt(1.W),0.U)
val lsu_idle_any_f = WireInit(UInt(1.W),0.U)
val ifu_miss_state_idle_f = WireInit(UInt(1.W),0.U)
val dbg_tlu_halted_f = WireInit(UInt(1.W),0.U)
val debug_halt_req_f = WireInit(UInt(1.W),0.U)
val debug_resume_req_f = WireInit(UInt(1.W),0.U)
val trigger_hit_dmode_r_d1 = WireInit(UInt(1.W),0.U)
val dcsr_single_step_done_f = WireInit(UInt(1.W),0.U)
val debug_halt_req_d1 = WireInit(UInt(1.W),0.U)
val request_debug_mode_r_d1 = WireInit(UInt(1.W),0.U)
val request_debug_mode_done_f = WireInit(UInt(1.W),0.U)
val dcsr_single_step_running_f = WireInit(UInt(1.W),0.U)
val dec_tlu_flush_pause_r_d1 = WireInit(UInt(1.W),0.U)
val dbg_halt_req_held = WireInit(UInt(1.W),0.U)
val debug_halt_req_ns = WireInit(UInt(1.W),0.U)
val internal_dbg_halt_mode = WireInit(UInt(1.W),0.U)
val core_empty = WireInit(UInt(1.W),0.U)
val dbg_halt_req_final = WireInit(UInt(1.W),0.U)
val debug_brkpt_status_ns = WireInit(UInt(1.W),0.U)
val mpc_debug_halt_ack_ns = WireInit(UInt(1.W),0.U)
val mpc_debug_run_ack_ns = WireInit(UInt(1.W),0.U)
val mpc_halt_state_ns = WireInit(UInt(1.W),0.U)
val mpc_run_state_ns = WireInit(UInt(1.W),0.U)
val dbg_halt_state_ns = WireInit(UInt(1.W),0.U)
val dbg_run_state_ns = WireInit(UInt(1.W),0.U)
val dbg_halt_state_f = WireInit(UInt(1.W),0.U)
val mpc_halt_state_f = WireInit(UInt(1.W),0.U)
val nmi_int_detected = WireInit(UInt(1.W),0.U)
val nmi_lsu_load_type = WireInit(UInt(1.W),0.U)
val nmi_lsu_store_type = WireInit(UInt(1.W),0.U)
val reset_delayed = WireInit(UInt(1.W),0.U)
val internal_dbg_halt_mode_f = WireInit(UInt(1.W),0.U)
val e5_valid = WireInit(UInt(1.W),0.U)
val ic_perr_r_d1 = WireInit(UInt(1.W),0.U)
val iccm_sbecc_r_d1 = WireInit(UInt(1.W),0.U)
val npc_r = WireInit(UInt(31.W),0.U)
val npc_r_d1 = WireInit(UInt(31.W),0.U)
@ -272,73 +272,73 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val dec_tlu_mpc_halted_only_ns = WireInit(UInt(1.W),0.U)
// tell dbg we are only MPC halted
dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f
val int_timers=Module(new dec_timer_ctl)
int_timers.io.free_clk :=io.free_clk
int_timers.io.scan_mode :=io.scan_mode
int_timers.io.dec_csr_wen_r_mod :=dec_csr_wen_r_mod
int_timers.io.dec_csr_rdaddr_d :=io.dec_csr_rdaddr_d
int_timers.io.dec_csr_wraddr_r :=io.dec_csr_wraddr_r
int_timers.io.dec_csr_wrdata_r :=io.dec_csr_wrdata_r
int_timers.io.csr_mitctl0 :=csr_pkt.csr_mitctl0
int_timers.io.csr_mitctl1 :=csr_pkt.csr_mitctl1
int_timers.io.csr_mitb0 :=csr_pkt.csr_mitb0
int_timers.io.csr_mitb1 :=csr_pkt.csr_mitb1
int_timers.io.csr_mitcnt0 :=csr_pkt.csr_mitcnt0
int_timers.io.csr_mitcnt1 :=csr_pkt.csr_mitcnt1
int_timers.io.dec_pause_state :=io.dec_pause_state
int_timers.io.dec_tlu_pmu_fw_halted :=dec_tlu_pmu_fw_halted
int_timers.io.internal_dbg_halt_timers:=internal_dbg_halt_timers
val int_timers = Module(new dec_timer_ctl)
int_timers.io.free_clk := io.free_clk
int_timers.io.scan_mode := io.scan_mode
int_timers.io.dec_csr_wen_r_mod := dec_csr_wen_r_mod
int_timers.io.dec_csr_rdaddr_d := io.dec_csr_rdaddr_d
int_timers.io.dec_csr_wraddr_r := io.dec_csr_wraddr_r
int_timers.io.dec_csr_wrdata_r := io.dec_csr_wrdata_r
int_timers.io.csr_mitctl0 := csr_pkt.csr_mitctl0
int_timers.io.csr_mitctl1 := csr_pkt.csr_mitctl1
int_timers.io.csr_mitb0 := csr_pkt.csr_mitb0
int_timers.io.csr_mitb1 := csr_pkt.csr_mitb1
int_timers.io.csr_mitcnt0 := csr_pkt.csr_mitcnt0
int_timers.io.csr_mitcnt1 := csr_pkt.csr_mitcnt1
int_timers.io.dec_pause_state := io.dec_pause_state
int_timers.io.dec_tlu_pmu_fw_halted := dec_tlu_pmu_fw_halted
int_timers.io.internal_dbg_halt_timers := internal_dbg_halt_timers
val dec_timer_rddata_d =int_timers.io.dec_timer_rddata_d
val dec_timer_read_d =int_timers.io.dec_timer_read_d
val dec_timer_t0_pulse =int_timers.io.dec_timer_t0_pulse
val dec_timer_t1_pulse =int_timers.io.dec_timer_t1_pulse
val dec_timer_rddata_d = int_timers.io.dec_timer_rddata_d
val dec_timer_read_d = int_timers.io.dec_timer_read_d
val dec_timer_t0_pulse = int_timers.io.dec_timer_t0_pulse
val dec_timer_t1_pulse = int_timers.io.dec_timer_t1_pulse
val clk_override = io.dec_tlu_dec_clk_override
// Async inputs to the core have to be sync'd to the core clock.
val syncro_ff=rvsyncss(Cat(io.nmi_int, io.timer_int, io.soft_int, io.i_cpu_halt_req, io.i_cpu_run_req, io.mpc_debug_halt_req, io.mpc_debug_run_req),io.free_clk)
val nmi_int_sync =syncro_ff(6)
val timer_int_sync =syncro_ff(5)
val soft_int_sync =syncro_ff(4)
val i_cpu_halt_req_sync =syncro_ff(3)
val i_cpu_run_req_sync =syncro_ff(2)
val mpc_debug_halt_req_sync_raw =syncro_ff(1)
val mpc_debug_run_req_sync =syncro_ff(0)
val syncro_ff = rvsyncss(Cat(io.nmi_int, io.timer_int, io.soft_int, io.i_cpu_halt_req, io.i_cpu_run_req, io.mpc_debug_halt_req, io.mpc_debug_run_req),io.free_clk)
val nmi_int_sync = syncro_ff(6)
val timer_int_sync = syncro_ff(5)
val soft_int_sync = syncro_ff(4)
val i_cpu_halt_req_sync = syncro_ff(3)
val i_cpu_run_req_sync = syncro_ff(2)
val mpc_debug_halt_req_sync_raw = syncro_ff(1)
val mpc_debug_run_req_sync = syncro_ff(0)
// for CSRs that have inpipe writes only
val csr_wr_clk=rvclkhdr(clock,(dec_csr_wen_r_mod | clk_override).asBool,io.scan_mode)
val lsu_r_wb_clk=rvclkhdr(clock,(io.lsu_error_pkt_r.valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode)
val csr_wr_clk = rvclkhdr(clock,(dec_csr_wen_r_mod | clk_override).asBool,io.scan_mode)
val lsu_r_wb_clk = rvclkhdr(clock,(io.lsu_error_pkt_r.valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode)
val e4_valid = io.dec_tlu_i0_valid_r
val e4e5_valid = e4_valid | e5_valid
val flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 | reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | ic_perr_r_d1 | iccm_sbecc_r | iccm_sbecc_r_d1 | clk_override
val e4e5_clk=rvclkhdr(clock,(e4e5_valid | clk_override).asBool,io.scan_mode)
val e4e5_int_clk=rvclkhdr(clock,(e4e5_valid | flush_clkvalid).asBool,io.scan_mode)
val e4e5_clk = rvclkhdr(clock,(e4e5_valid | clk_override).asBool,io.scan_mode)
val e4e5_int_clk = rvclkhdr(clock,(e4e5_valid | flush_clkvalid).asBool,io.scan_mode)
val iccm_repair_state_d1 =withClock(io.free_clk){RegNext(iccm_repair_state_ns,0.U)}
ic_perr_r_d1 :=withClock(io.free_clk){RegNext(ic_perr_r,0.U)}
iccm_sbecc_r_d1 :=withClock(io.free_clk){RegNext(iccm_sbecc_r,0.U)}
e5_valid :=withClock(io.free_clk){RegNext(e4_valid,0.U)}
internal_dbg_halt_mode_f :=withClock(io.free_clk){RegNext(internal_dbg_halt_mode,0.U)}
val lsu_pmu_load_external_r =withClock(io.free_clk){RegNext(io.lsu_tlu.lsu_pmu_load_external_m,0.U)}
val lsu_pmu_store_external_r =withClock(io.free_clk){RegNext(io.lsu_tlu.lsu_pmu_store_external_m,0.U)}
val tlu_flush_lower_r_d1 =withClock(io.free_clk){RegNext(tlu_flush_lower_r,0.U)}
io.dec_tlu_i0_kill_writeb_wb :=withClock(io.free_clk){RegNext(tlu_i0_kill_writeb_r,0.U)}
val internal_dbg_halt_mode_f2 =withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)}
io.tlu_mem.dec_tlu_force_halt :=withClock(io.free_clk){RegNext(force_halt,0.U)}
val iccm_repair_state_d1 = withClock(io.free_clk){RegNext(iccm_repair_state_ns,0.U)}
ic_perr_r_d1 := withClock(io.free_clk){RegNext(ic_perr_r,0.U)}
iccm_sbecc_r_d1 := withClock(io.free_clk){RegNext(iccm_sbecc_r,0.U)}
e5_valid := withClock(io.free_clk){RegNext(e4_valid,0.U)}
internal_dbg_halt_mode_f := withClock(io.free_clk){RegNext(internal_dbg_halt_mode,0.U)}
val lsu_pmu_load_external_r = withClock(io.free_clk){RegNext(io.lsu_tlu.lsu_pmu_load_external_m,0.U)}
val lsu_pmu_store_external_r = withClock(io.free_clk){RegNext(io.lsu_tlu.lsu_pmu_store_external_m,0.U)}
val tlu_flush_lower_r_d1 = withClock(io.free_clk){RegNext(tlu_flush_lower_r,0.U)}
io.dec_tlu_i0_kill_writeb_wb := withClock(io.free_clk){RegNext(tlu_i0_kill_writeb_r,0.U)}
val internal_dbg_halt_mode_f2 = withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)}
io.tlu_mem.dec_tlu_force_halt := withClock(io.free_clk){RegNext(force_halt,0.U)}
io.dec_tlu_i0_kill_writeb_r :=tlu_i0_kill_writeb_r
val reset_detect =withClock(io.free_clk){RegNext(1.U(1.W),0.U)}
val reset_detected =withClock(io.free_clk){RegNext(reset_detect,0.U)}
reset_delayed :=reset_detect ^ reset_detected
io.dec_tlu_i0_kill_writeb_r := tlu_i0_kill_writeb_r
val reset_detect = withClock(io.free_clk){RegNext(1.U(1.W),0.U)}
val reset_detected = withClock(io.free_clk){RegNext(reset_detect,0.U)}
reset_delayed := reset_detect ^ reset_detected
val nmi_int_delayed =withClock(io.free_clk){RegNext(nmi_int_sync,0.U)}
val nmi_int_detected_f =withClock(io.free_clk){RegNext(nmi_int_detected,0.U)}
val nmi_lsu_load_type_f =withClock(io.free_clk){RegNext(nmi_lsu_load_type,0.U)}
val nmi_lsu_store_type_f =withClock(io.free_clk){RegNext(nmi_lsu_store_type,0.U)}
val nmi_int_delayed = withClock(io.free_clk){RegNext(nmi_int_sync,0.U)}
val nmi_int_detected_f = withClock(io.free_clk){RegNext(nmi_int_detected,0.U)}
val nmi_lsu_load_type_f = withClock(io.free_clk){RegNext(nmi_lsu_load_type,0.U)}
val nmi_lsu_store_type_f = withClock(io.free_clk){RegNext(nmi_lsu_store_type,0.U)}
// Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared
@ -355,16 +355,16 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
// fast ints in progress have priority
val mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1
val mpc_debug_halt_req_sync_f =withClock(io.free_clk){RegNext(mpc_debug_halt_req_sync,0.U)}
val mpc_debug_run_req_sync_f =withClock(io.free_clk){RegNext(mpc_debug_run_req_sync,0.U)}
mpc_halt_state_f :=withClock(io.free_clk){RegNext(mpc_halt_state_ns,0.U)}
val mpc_run_state_f =withClock(io.free_clk){RegNext(mpc_run_state_ns,0.U)}
val debug_brkpt_status_f =withClock(io.free_clk){RegNext(debug_brkpt_status_ns,0.U)}
val mpc_debug_halt_ack_f =withClock(io.free_clk){RegNext(mpc_debug_halt_ack_ns,0.U)}
val mpc_debug_run_ack_f =withClock(io.free_clk){RegNext(mpc_debug_run_ack_ns,0.U)}
dbg_halt_state_f :=withClock(io.free_clk){RegNext(dbg_halt_state_ns,0.U)}
val dbg_run_state_f =withClock(io.free_clk){RegNext(dbg_run_state_ns,0.U)}
io.dec_tlu_mpc_halted_only :=withClock(io.free_clk){RegNext(dec_tlu_mpc_halted_only_ns,0.U)}
val mpc_debug_halt_req_sync_f = withClock(io.free_clk){RegNext(mpc_debug_halt_req_sync,0.U)}
val mpc_debug_run_req_sync_f = withClock(io.free_clk){RegNext(mpc_debug_run_req_sync,0.U)}
mpc_halt_state_f := withClock(io.free_clk){RegNext(mpc_halt_state_ns,0.U)}
val mpc_run_state_f = withClock(io.free_clk){RegNext(mpc_run_state_ns,0.U)}
val debug_brkpt_status_f = withClock(io.free_clk){RegNext(debug_brkpt_status_ns,0.U)}
val mpc_debug_halt_ack_f = withClock(io.free_clk){RegNext(mpc_debug_halt_ack_ns,0.U)}
val mpc_debug_run_ack_f = withClock(io.free_clk){RegNext(mpc_debug_run_ack_ns,0.U)}
dbg_halt_state_f := withClock(io.free_clk){RegNext(dbg_halt_state_ns,0.U)}
val dbg_run_state_f = withClock(io.free_clk){RegNext(dbg_run_state_ns,0.U)}
io.dec_tlu_mpc_halted_only := withClock(io.free_clk){RegNext(dec_tlu_mpc_halted_only_ns,0.U)}
// turn level sensitive requests into pulses
@ -444,24 +444,24 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f
dec_tlu_flush_noredir_r_d1 :=withClock(io.free_clk){RegNext(io.tlu_ifc.dec_tlu_flush_noredir_wb,0.U)}
halt_taken_f :=withClock(io.free_clk){RegNext(halt_taken,0.U)}
lsu_idle_any_f :=withClock(io.free_clk){RegNext(io.lsu_idle_any,0.U)}
ifu_miss_state_idle_f :=withClock(io.free_clk){RegNext(io.tlu_mem.ifu_miss_state_idle,0.U)}
dbg_tlu_halted_f :=withClock(io.free_clk){RegNext(dbg_tlu_halted,0.U)}
io.dec_tlu_resume_ack :=withClock(io.free_clk){RegNext(resume_ack_ns,0.U)}
debug_halt_req_f :=withClock(io.free_clk){RegNext(debug_halt_req_ns,0.U)}
debug_resume_req_f :=withClock(io.free_clk){RegNext(debug_resume_req,0.U)}
trigger_hit_dmode_r_d1 :=withClock(io.free_clk){RegNext(trigger_hit_dmode_r,0.U)}
dcsr_single_step_done_f :=withClock(io.free_clk){RegNext(dcsr_single_step_done,0.U)}
debug_halt_req_d1 :=withClock(io.free_clk){RegNext(debug_halt_req,0.U)}
val dec_tlu_wr_pause_r_d1 =withClock(io.free_clk){RegNext(io.dec_tlu_wr_pause_r,0.U)}
val dec_pause_state_f =withClock(io.free_clk){RegNext(io.dec_pause_state,0.U)}
request_debug_mode_r_d1 :=withClock(io.free_clk){RegNext(request_debug_mode_r,0.U)}
request_debug_mode_done_f :=withClock(io.free_clk){RegNext(request_debug_mode_done,0.U)}
dcsr_single_step_running_f :=withClock(io.free_clk){RegNext(dcsr_single_step_running,0.U)}
dec_tlu_flush_pause_r_d1 :=withClock(io.free_clk){RegNext(io.dec_tlu_flush_pause_r,0.U)}
dbg_halt_req_held :=withClock(io.free_clk){RegNext(dbg_halt_req_held_ns,0.U)}
dec_tlu_flush_noredir_r_d1 := withClock(io.free_clk){RegNext(io.tlu_ifc.dec_tlu_flush_noredir_wb,0.U)}
halt_taken_f := withClock(io.free_clk){RegNext(halt_taken,0.U)}
lsu_idle_any_f := withClock(io.free_clk){RegNext(io.lsu_idle_any,0.U)}
ifu_miss_state_idle_f := withClock(io.free_clk){RegNext(io.tlu_mem.ifu_miss_state_idle,0.U)}
dbg_tlu_halted_f := withClock(io.free_clk){RegNext(dbg_tlu_halted,0.U)}
io.dec_tlu_resume_ack := withClock(io.free_clk){RegNext(resume_ack_ns,0.U)}
debug_halt_req_f := withClock(io.free_clk){RegNext(debug_halt_req_ns,0.U)}
debug_resume_req_f := withClock(io.free_clk){RegNext(debug_resume_req,0.U)}
trigger_hit_dmode_r_d1 := withClock(io.free_clk){RegNext(trigger_hit_dmode_r,0.U)}
dcsr_single_step_done_f := withClock(io.free_clk){RegNext(dcsr_single_step_done,0.U)}
debug_halt_req_d1 := withClock(io.free_clk){RegNext(debug_halt_req,0.U)}
val dec_tlu_wr_pause_r_d1 = withClock(io.free_clk){RegNext(io.dec_tlu_wr_pause_r,0.U)}
val dec_pause_state_f = withClock(io.free_clk){RegNext(io.dec_pause_state,0.U)}
request_debug_mode_r_d1 := withClock(io.free_clk){RegNext(request_debug_mode_r,0.U)}
request_debug_mode_done_f := withClock(io.free_clk){RegNext(request_debug_mode_done,0.U)}
dcsr_single_step_running_f := withClock(io.free_clk){RegNext(dcsr_single_step_running,0.U)}
dec_tlu_flush_pause_r_d1 := withClock(io.free_clk){RegNext(io.dec_tlu_flush_pause_r,0.U)}
dbg_halt_req_held := withClock(io.free_clk){RegNext(dbg_halt_req_held_ns,0.U)}
io.dec_tlu_debug_stall := debug_halt_req_f
@ -560,23 +560,21 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
// o_cpu_halt_status _______________|---------------------|_________
// i_cpu_run_req ______|----------|____
// o_cpu_run_ack ____________|------|________
//
// debug mode has priority, ignore PMU/FW halt/run while in debug mode
val i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~io.dec_tlu_debug_mode & ~ext_int_freeze_d1
val i_cpu_run_req_sync_qual = i_cpu_run_req_sync & ~io.dec_tlu_debug_mode & pmu_fw_tlu_halted_f & ~ext_int_freeze_d1
val i_cpu_halt_req_d1 =withClock(io.free_clk){RegNext(i_cpu_halt_req_sync_qual,0.U)}
val i_cpu_run_req_d1_raw =withClock(io.free_clk){RegNext(i_cpu_run_req_sync_qual,0.U)}
io.o_cpu_halt_status :=withClock(io.free_clk){RegNext(cpu_halt_status,0.U)}
io.o_cpu_halt_ack :=withClock(io.free_clk){RegNext(cpu_halt_ack,0.U)}
io.o_cpu_run_ack :=withClock(io.free_clk){RegNext(cpu_run_ack,0.U)}
val internal_pmu_fw_halt_mode_f=withClock(io.free_clk){RegNext(internal_pmu_fw_halt_mode,0.U)}
pmu_fw_halt_req_f :=withClock(io.free_clk){RegNext(pmu_fw_halt_req_ns,0.U)}
pmu_fw_tlu_halted_f :=withClock(io.free_clk){RegNext(pmu_fw_tlu_halted,0.U)}
int_timer0_int_hold_f :=withClock(io.free_clk){RegNext(int_timer0_int_hold,0.U)}
int_timer1_int_hold_f :=withClock(io.free_clk){RegNext(int_timer1_int_hold,0.U)}
val i_cpu_halt_req_d1 = withClock(io.free_clk){RegNext(i_cpu_halt_req_sync_qual,0.U)}
val i_cpu_run_req_d1_raw = withClock(io.free_clk){RegNext(i_cpu_run_req_sync_qual,0.U)}
io.o_cpu_halt_status := withClock(io.free_clk){RegNext(cpu_halt_status,0.U)}
io.o_cpu_halt_ack := withClock(io.free_clk){RegNext(cpu_halt_ack,0.U)}
io.o_cpu_run_ack := withClock(io.free_clk){RegNext(cpu_run_ack,0.U)}
val internal_pmu_fw_halt_mode_f = withClock(io.free_clk){RegNext(internal_pmu_fw_halt_mode,0.U)}
pmu_fw_halt_req_f := withClock(io.free_clk){RegNext(pmu_fw_halt_req_ns,0.U)}
pmu_fw_tlu_halted_f := withClock(io.free_clk){RegNext(pmu_fw_tlu_halted,0.U)}
int_timer0_int_hold_f := withClock(io.free_clk){RegNext(int_timer0_int_hold,0.U)}
int_timer1_int_hold_f := withClock(io.free_clk){RegNext(int_timer1_int_hold,0.U)}
// only happens if we aren't in dgb_halt
@ -739,10 +737,10 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
if(FAST_INTERRUPT_REDIRECT) {
take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)}
take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)}
take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)}
ext_int_freeze_d1 :=withClock(io.free_clk){RegNext(ext_int_freeze,0.U)}
take_ext_int_start_d1 := withClock(io.free_clk){RegNext(take_ext_int_start,0.U)}
take_ext_int_start_d2 := withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)}
take_ext_int_start_d3 := withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)}
ext_int_freeze_d1 := withClock(io.free_clk){RegNext(ext_int_freeze,0.U)}
take_ext_int_start := ext_int_ready & ~block_interrupts;
ext_int_freeze := take_ext_int_start | take_ext_int_start_d1 | take_ext_int_start_d2 | take_ext_int_start_d3
@ -797,21 +795,20 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this
io.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1
// io.tlu_mem.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
io.tlu_exu.dec_tlu_flush_lower_r := tlu_flush_lower_r
io.tlu_exu.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this
// this is used to capture mepc, etc.
val exc_or_int_valid_r = lsu_exc_valid_r | i0_exception_valid_r | interrupt_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r)
interrupt_valid_r_d1 :=withClock(e4e5_int_clk){RegNext(interrupt_valid_r,0.U)}
val i0_exception_valid_r_d1 =withClock(e4e5_int_clk){RegNext(i0_exception_valid_r,0.U)}
exc_or_int_valid_r_d1 :=withClock(e4e5_int_clk){RegNext(exc_or_int_valid_r,0.U)}
val exc_cause_wb =withClock(e4e5_int_clk){RegNext(exc_cause_r,0.U)}
val i0_valid_wb =withClock(e4e5_int_clk){RegNext((tlu_i0_commit_cmt & ~illegal_r),0.U)}
val trigger_hit_r_d1 =withClock(e4e5_int_clk){RegNext(i0_trigger_hit_r,0.U)}
take_nmi_r_d1 :=withClock(e4e5_int_clk){RegNext(take_nmi,0.U)}
pause_expired_wb :=withClock(e4e5_int_clk){RegNext(pause_expired_r,0.U)}
interrupt_valid_r_d1 := withClock(e4e5_int_clk){RegNext(interrupt_valid_r,0.U)}
val i0_exception_valid_r_d1 = withClock(e4e5_int_clk){RegNext(i0_exception_valid_r,0.U)}
exc_or_int_valid_r_d1 := withClock(e4e5_int_clk){RegNext(exc_or_int_valid_r,0.U)}
val exc_cause_wb = withClock(e4e5_int_clk){RegNext(exc_cause_r,0.U)}
val i0_valid_wb = withClock(e4e5_int_clk){RegNext((tlu_i0_commit_cmt & ~illegal_r),0.U)}
val trigger_hit_r_d1 = withClock(e4e5_int_clk){RegNext(i0_trigger_hit_r,0.U)}
take_nmi_r_d1 := withClock(e4e5_int_clk){RegNext(take_nmi,0.U)}
pause_expired_wb := withClock(e4e5_int_clk){RegNext(pause_expired_r,0.U)}
val csr=Module(new csr_tlu)
csr.io.free_clk := io.free_clk
@ -824,21 +821,21 @@ val csr=Module(new csr_tlu)
csr.io.dec_i0_decode_d := io.dec_i0_decode_d
csr.io.ifu_ic_debug_rd_data_valid := io.tlu_mem.ifu_ic_debug_rd_data_valid
csr.io.ifu_pmu_bus_trxn := io.tlu_mem.ifu_pmu_bus_trxn
csr.io.dma_iccm_stall_any :=io.tlu_dma.dma_iccm_stall_any
csr.io.dma_dccm_stall_any :=io.tlu_dma.dma_dccm_stall_any
csr.io.lsu_store_stall_any :=io.lsu_store_stall_any
csr.io.dec_pmu_presync_stall :=io.dec_pmu_presync_stall
csr.io.dec_pmu_postsync_stall :=io.dec_pmu_postsync_stall
csr.io.dec_pmu_decode_stall :=io.dec_pmu_decode_stall
csr.io.ifu_pmu_fetch_stall :=io.tlu_ifc.ifu_pmu_fetch_stall
csr.io.dec_tlu_packet_r :=io.dec_tlu_packet_r
csr.io.exu_pmu_i0_br_ataken :=io.tlu_exu.exu_pmu_i0_br_ataken
csr.io.exu_pmu_i0_br_misp :=io.tlu_exu.exu_pmu_i0_br_misp
csr.io.dec_pmu_instr_decoded :=io.dec_pmu_instr_decoded
csr.io.ifu_pmu_instr_aligned :=io.ifu_pmu_instr_aligned
csr.io.exu_pmu_i0_pc4 :=io.tlu_exu.exu_pmu_i0_pc4
csr.io.ifu_pmu_ic_miss :=io.tlu_mem.ifu_pmu_ic_miss
csr.io.ifu_pmu_ic_hit :=io.tlu_mem.ifu_pmu_ic_hit
csr.io.dma_iccm_stall_any := io.tlu_dma.dma_iccm_stall_any
csr.io.dma_dccm_stall_any := io.tlu_dma.dma_dccm_stall_any
csr.io.lsu_store_stall_any := io.lsu_store_stall_any
csr.io.dec_pmu_presync_stall := io.dec_pmu_presync_stall
csr.io.dec_pmu_postsync_stall := io.dec_pmu_postsync_stall
csr.io.dec_pmu_decode_stall := io.dec_pmu_decode_stall
csr.io.ifu_pmu_fetch_stall := io.tlu_ifc.ifu_pmu_fetch_stall
csr.io.dec_tlu_packet_r := io.dec_tlu_packet_r
csr.io.exu_pmu_i0_br_ataken := io.tlu_exu.exu_pmu_i0_br_ataken
csr.io.exu_pmu_i0_br_misp := io.tlu_exu.exu_pmu_i0_br_misp
csr.io.dec_pmu_instr_decoded := io.dec_pmu_instr_decoded
csr.io.ifu_pmu_instr_aligned := io.ifu_pmu_instr_aligned
csr.io.exu_pmu_i0_pc4 := io.tlu_exu.exu_pmu_i0_pc4
csr.io.ifu_pmu_ic_miss := io.tlu_mem.ifu_pmu_ic_miss
csr.io.ifu_pmu_ic_hit := io.tlu_mem.ifu_pmu_ic_hit
csr.io.dec_csr_wen_r := io.dec_csr_wen_r
csr.io.dec_tlu_dbg_halted := io.dec_tlu_dbg_halted
csr.io.dma_pmu_dccm_write := io.tlu_dma.dma_pmu_dccm_write
@ -1165,8 +1162,6 @@ trait CSRs{
val MHPME_DMA_WRITE_ALL = 514.U // OOP
val MHPME_DMA_READ_DCCM = 515.U // OOP
val MHPME_DMA_WRITE_DCCM = 516.U // OOP
}
class CSR_IO extends Bundle with lib {
val free_clk = Input(Clock())
@ -1200,8 +1195,6 @@ class CSR_IO extends Bundle with lib {
val dec_tlu_i0_exc_valid_wb1 = Output(UInt(1.W))
val dec_tlu_i0_valid_wb1 = Output(UInt(1.W))
val dec_csr_wen_r = Input(UInt(1.W))
//val dec_tlu_force_halt = Output(UInt(1.W))
//val dec_tlu_flush_extint = Output(UInt(1.W))
val dec_tlu_mtval_wb1 = Output(UInt(32.W))
val dec_tlu_exc_cause_wb1 = Output(UInt(5.W))
val dec_tlu_perfcnt0 = Output(UInt(1.W))
@ -1226,17 +1219,7 @@ class CSR_IO extends Bundle with lib {
val dec_tlu_pic_clk_override = Output(UInt(1.W))
val dec_tlu_dccm_clk_override = Output(UInt(1.W))
val dec_tlu_icm_clk_override = Output(UInt(1.W))
//val dec_csr_legal_d = Output(UInt(1.W))
val dec_csr_rddata_d = Output(UInt(32.W))
//val dec_tlu_postsync_d = Output(UInt(1.W))
//val dec_tlu_presync_d = Output(UInt(1.W))
//val dec_tlu_flush_pause_r = Output(UInt(1.W))
//val dec_tlu_flush_lower_r = Output(UInt(1.W))
//val dec_tlu_i0_kill_writeb_r = Output(UInt(1.W))
//val dec_tlu_flush_lower_wb = Output(UInt(1.W))
//val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W))
// val dec_tlu_flush_leak_one_wb = Output(UInt(1.W))
//val dec_tlu_debug_stall = Output(UInt(1.W))
val dec_tlu_pipelining_disable = Output(UInt(1.W))
val dec_tlu_wr_pause_r = Output(UInt(1.W))
val ifu_pmu_bus_busy = Input(UInt(1.W))
@ -1396,7 +1379,6 @@ val wr_mcycleh_r = WireInit(UInt(1.W), 0.U)
val force_halt_ctr_f = WireInit(UInt(32.W),0.U)
val mdccmect_inc = WireInit(UInt(27.W),0.U)
val miccmect_inc = WireInit(UInt(27.W),0.U)
//val fw_halted = WireInit(UInt(1.W),0.U)
val micect_inc = WireInit(UInt(27.W),0.U)
val mdseac_en = WireInit(UInt(1.W),0.U)
val mie = WireInit(UInt(6.W),0.U)

34
src/main/scala/exu/exu.scala
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@ -48,9 +48,9 @@ class exu extends Module with lib with RequireAsyncReset{
val i0_pred_correct_upper_d = Wire(UInt(1.W))
val i0_flush_upper_d = Wire(UInt(1.W))
io.exu_bp.exu_mp_pkt.bits.prett :=0.U
io.exu_bp.exu_mp_pkt.bits.br_start_error:=0.U
io.exu_bp.exu_mp_pkt.bits.br_error :=0.U
io.exu_bp.exu_mp_pkt.valid :=0.U
io.exu_bp.exu_mp_pkt.bits.br_start_error :=0.U
io.exu_bp.exu_mp_pkt.bits.br_error := 0.U
io.exu_bp.exu_mp_pkt.valid := 0.U
i0_pp_r.bits.toffset := 0.U
val x_data_en = io.dec_exu.decode_exu.dec_data_en(1)
@ -138,10 +138,10 @@ class exu extends Module with lib with RequireAsyncReset{
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
))
csr_rs1_in_d := Mux( io.dec_exu.dec_alu.dec_csr_ren_d.asBool, i0_rs1_d, io.dec_exu.decode_exu.exu_csr_rs1_x)
csr_rs1_in_d := Mux(io.dec_exu.dec_alu.dec_csr_ren_d.asBool, i0_rs1_d, io.dec_exu.decode_exu.exu_csr_rs1_x)
val i_alu=Module(new exu_alu_ctl)
val i_alu=Module(new exu_alu_ctl())
i_alu.io.dec_alu <> io.dec_exu.dec_alu
i_alu.io.scan_mode :=io.scan_mode
i_alu.io.enable :=x_ctl_en
@ -159,21 +159,21 @@ class exu extends Module with lib with RequireAsyncReset{
i0_predict_p_d :=i_alu.io.predict_p_out
i0_pred_correct_upper_d :=i_alu.io.pred_correct_out
val i_mul=Module(new exu_mul_ctl)
i_mul.io.scan_mode :=io.scan_mode
i_mul.io.mul_p :=io.dec_exu.decode_exu.mul_p
i_mul.io.rs1_in :=muldiv_rs1_d
i_mul.io.rs2_in :=muldiv_rs2_d
val mul_result_x =i_mul.io.result_x
val i_mul = Module(new exu_mul_ctl())
i_mul.io.scan_mode := io.scan_mode
i_mul.io.mul_p := io.dec_exu.decode_exu.mul_p
i_mul.io.rs1_in := muldiv_rs1_d
i_mul.io.rs2_in := muldiv_rs2_d
val mul_result_x = i_mul.io.result_x
val i_div=Module(new exu_div_ctl)
val i_div = Module(new exu_div_ctl())
i_div.io.dec_div <> io.dec_exu.dec_div
i_div.io.scan_mode :=io.scan_mode
i_div.io.scan_mode := io.scan_mode
i_div.io.dividend :=muldiv_rs1_d
i_div.io.divisor :=muldiv_rs2_d
io.exu_div_wren :=i_div.io.exu_div_wren
io.exu_div_result :=i_div.io.exu_div_result
i_div.io.dividend := muldiv_rs1_d
i_div.io.divisor := muldiv_rs2_d
io.exu_div_wren := i_div.io.exu_div_wren
io.exu_div_result := i_div.io.exu_div_result
io.dec_exu.decode_exu.exu_i0_result_x := Mux(mul_valid_x.asBool, mul_result_x, alu_result_x)
i0_predict_newp_d := io.dec_exu.decode_exu.dec_i0_predict_p_d

28
src/main/scala/include/bundle.scala
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@ -34,7 +34,6 @@ class tlu_dma extends Bundle{
class dec_bp extends Bundle{
val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t))
// val dec_tlu_flush_lower_wb = Input(Bool())
val dec_tlu_flush_leak_one_wb = Input(Bool())
val dec_tlu_bpred_disable = Input(Bool())
}
@ -71,8 +70,8 @@ class ahb_out extends Bundle{
val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data
}
class ahb_channel extends Bundle{
val in = new ahb_in
val out = new ahb_out
val in = new ahb_in()
val out = new ahb_out()
}
class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{
val aw = Decoupled(new write_addr(BUS_TAG))
@ -272,13 +271,16 @@ class ifu_dec extends Bundle{
val dec_ifc = new dec_ifc
val dec_bp = new dec_bp
}
class exu_ifu extends Bundle{
val exu_bp = Flipped(new exu_bp())
}
class ifu_dma extends Bundle{
val dma_ifc = new dma_ifc
val dma_mem_ctl = new dma_mem_ctl
}
class dma_mem_ctl extends Bundle{
val dma_iccm_req = Input(Bool())
val dma_mem_addr = Input(UInt(32.W))
@ -287,6 +289,7 @@ class dma_mem_ctl extends Bundle{
val dma_mem_wdata = Input(UInt(64.W))
val dma_mem_tag = Input(UInt(3.W))
}
class dma_ifc extends Bundle{
val dma_iccm_stall_any = Input(Bool())
}
@ -301,14 +304,11 @@ class trace_pkt_t extends Bundle{
val rv_i_tval_ip = Output(UInt(32.W) )
}
class dec_dbg extends Bundle{
val dbg_ib = new dbg_ib
val dbg_dctl = new dbg_dctl
}
class dbg_ib extends Bundle{
val dbg_cmd_valid = Input(Bool()) // debugger abstract command valid
val dbg_cmd_write = Input(Bool()) // command is a write
@ -320,8 +320,6 @@ class dbg_dctl extends Bundle{
val dbg_cmd_wrdata = Input(UInt(32.W)) // command write data, for fence/fence_i
}
class dec_alu extends Bundle {
val dec_i0_alu_decode_d = Input(UInt(1.W)) // Valid
val dec_csr_ren_d = Input(Bool()) // extra decode
@ -418,7 +416,6 @@ object inst_pkt_t extends Enumeration{
}
class load_cam_pkt_t extends Bundle {
//val valid = UInt(1.W)
val wb = UInt(1.W)
val tag = UInt(3.W)
val rd = UInt(5.W)
@ -431,7 +428,6 @@ class rets_pkt_t extends Bundle {
}
class br_pkt_t extends Bundle {
// val valid = UInt(1.W)
val toffset = UInt(12.W)
val hist = UInt(2.W)
val br_error = UInt(1.W)
@ -444,7 +440,6 @@ class br_pkt_t extends Bundle {
class br_tlu_pkt_t extends Bundle {
// val valid = UInt(1.W)
val hist = UInt(2.W)
val br_error = UInt(1.W)
val br_start_error = UInt(1.W)
@ -459,7 +454,6 @@ class predict_pkt_t extends Bundle {
val pc4 = UInt(1.W)
val hist = UInt(2.W)
val toffset = UInt(12.W)
// val valid = UInt(1.W)
val br_error = UInt(1.W)
val br_start_error = UInt(1.W)
val prett = UInt(31.W)
@ -477,7 +471,7 @@ class trap_pkt_t extends Bundle {
val icaf_type = UInt(2.W)
val fence_i = UInt(1.W)
val i0trigger = UInt(4.W)
val pmu_i0_itype =UInt(4.W) //new inst_pkt_t //pmu-instructiontype
val pmu_i0_itype =UInt(4.W) //pmu-instructiontype
val pmu_i0_br_unpred = UInt(1.W) //pmu
val pmu_divide = UInt(1.W)
val pmu_lsu_misaligned = UInt(1.W)
@ -489,7 +483,6 @@ class dest_pkt_t extends Bundle {
val i0store = UInt(1.W)
val i0div = UInt(1.W)
val i0v = UInt(1.W)
// val i0valid = UInt(1.W)
val csrwen = UInt(1.W)
val csrwonly = UInt(1.W)
val csrwaddr = UInt(12.W)
@ -543,11 +536,9 @@ class lsu_pkt_t extends Bundle {
val store_data_bypass_d = Bool()
val load_ldst_bypass_d = Bool()
val store_data_bypass_m = Bool()
// val valid = Bool()
}
class lsu_error_pkt_t extends Bundle {
// val exc_valid = UInt(1.W)
val single_ecc_error = UInt(1.W)
val inst_type = UInt(1.W) //0: Load, 1: Store
val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault
@ -609,7 +600,6 @@ class dec_pkt_t extends Bundle {
}
class mul_pkt_t extends Bundle {
// val valid = UInt(1.W)
val rs1_sign = UInt(1.W)
val rs2_sign = UInt(1.W)
val low = UInt(1.W)
@ -631,7 +621,6 @@ class mul_pkt_t extends Bundle {
}
class div_pkt_t extends Bundle {
// val valid = UInt(1.W)
val unsign = UInt(1.W)
val rem = UInt(1.W)
}
@ -640,7 +629,6 @@ class ccm_ext_in_pkt_t extends Bundle {
val TEST1 = UInt(1.W)
val RME = UInt(1.W)
val RM = UInt(4.W)
val LS = UInt(1.W)
val DS = UInt(1.W)
val SD = UInt(1.W)

4
src/main/scala/lib/param.scala
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@ -21,8 +21,8 @@ trait param {
val BTB_INDEX3_HI = 0x19
val BTB_INDEX3_LO = 0x12
val BTB_SIZE = 0x200
val BUILD_AHB_LITE = 0x0
val BUILD_AXI4 = 0x1
val BUILD_AHB_LITE = 0x1
val BUILD_AXI4 = 0x0
val BUILD_AXI_NATIVE = 0x1
val BUS_PRTY_DEFAULT = 0x3
val DATA_ACCESS_ADDR0 = 0x00000000

2
src/main/scala/lsu/lsu_ecc.scala
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@ -71,8 +71,6 @@ class lsu_ecc extends Module with lib with RequireAsyncReset {
val dccm_wdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
val dccm_rdata_hi_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
val dccm_rdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
// val dccm_wdata_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
//val dccm_wdata_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
val dccm_data_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
val dccm_data_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
val double_ecc_error_hi_m = WireInit(Bool(),init = 0.U)

3
src/main/scala/lsu/lsu_stbuf.scala
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@ -264,7 +264,4 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset {
val stbuf_fwdpipe3_hi = Mux(ld_byte_rhit_hi(2),ld_fwddata_rpipe_hi(23,16),stbuf_fwddata_hi_pre_m(23,16))
val stbuf_fwdpipe4_hi = Mux(ld_byte_rhit_hi(3),ld_fwddata_rpipe_hi(31,24),stbuf_fwddata_hi_pre_m(31,24))
io.stbuf_fwddata_hi_m := Cat(stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi,stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi)
}

1
src/main/scala/lsu/lsu_trigger.scala
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@ -18,5 +18,4 @@ class lsu_trigger extends Module with RequireAsyncReset with lib {
io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.bits.store)|
(io.trigger_pkt_any(i).load & io.lsu_pkt_m.bits.load & !io.trigger_pkt_any(i).select) )&
rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_pkt.asBool())).reverse.reduce(Cat(_,_))
}

6
src/main/scala/quasar_wrapper.scala
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@ -15,7 +15,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
// AXI Signals
val lsu_brg = bridge_gen(LSU_BUS_TAG, false)
val ifu_brg = bridge_gen(IFU_BUS_TAG, false)
val sb_brg = bridge_gen(SB_BUS_TAG, false)
val sb_brg = bridge_gen(SB_BUS_TAG , false)
val dma_brg = bridge_gen(DMA_BUS_TAG, true)
val lsu_bus_clk_en = Input(Bool())
@ -71,8 +71,6 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
dmi_wrapper.io.core_clk := clock
dmi_wrapper.io.jtag_id := io.jtag_id
dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
dmi_wrapper.io.core_rst_n := io.dbg_rst_l
core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
@ -144,7 +142,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
// Outputs
val core_rst_l = core.io.core_rst_l
io.rv_trace_pkt := core.io.rv_trace_pkt
io.rv_trace_pkt <> core.io.rv_trace_pkt
// external halt/run interface
io.o_cpu_halt_ack := core.io.o_cpu_halt_ack

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