182 lines
8.0 KiB
Markdown
182 lines
8.0 KiB
Markdown
# Quasar RISC-V Core from Lampro Mellon
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This repository contains the Quasar Core design in CHISEL.
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## Background
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Quasar is a Chiselified version of EL2 SweRV RISC-V Core.
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## Directory Structure
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├── project
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│ ├── project
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│ └── target
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├── src
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│ ├── main
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│ ├── resource
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│ └── vsrc # Blackbox files
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│ └── scala # Design root dir
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│ ├── dbg # Debugger
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│ ├── dec # Decode, Registers and Exceptions
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│ ├── dmi # DMI block
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│ ├── exu # EXU (ALU/MUL/DIV)
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│ ├── ifu # Fetch & Branch Prediction
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│ ├── include # Bundles file
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│ ├── lib # Bridges and Libraries
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│ ├── lsu # Load/Store
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│ ├── snapshot # Configurations Dir
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│ ├── el2_dma_ctrl.scala #
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│ ├── el2_pic_ctl.scala #
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│ └── el2_swerv.scala #
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│ └── test
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│ └── scala
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│ └── lib
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├── Docs # Spec. document
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├── rtl # Chisel generated verilog
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│ ├── ***** #
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│ └── ***** #
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├── target
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│ ├── scala-2.12
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│ └── streams
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├── test_run_dir
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└── build.sbt # Scala-based DSL
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## Dependencies
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- Verilator **(4.030 or later)** must be installed on the system if running with verilator.
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- RISCV tool chain (based on gcc version 7.3 or higher) must be
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installed so that it can be used to prepare RISCV binaries to run.
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- Sbt **(1.3.13 or later)** must be installed on the system.
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## Quickstart guide
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1. Clone the repository
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2. Setup RV_ROOT to point to the path in your local filesystem
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3. Determine your configuration {optional}
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4. Run make with Makefile
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## Release Notes for this version
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Please see [release notes](release-notes.md) for changes and bug fixes in this version of Quasar.
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### Configurations
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Quasar can be configured by running the `****************************` script:
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`% ****************************` for detailed help options
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For example to build with a DCCM of size 64 Kb:
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`% *******************************`
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This will update the **default** snapshot in $RV_ROOT/configs/snapshots/default/ with parameters for a 64K DCCM.
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Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot *dccm64* and refer to it during the build.
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There are 4 predefined target configurations: `default`, `default_mt`, `typical_pd` and `high_perf` that can be selected via
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the `-target=name` option to swerv.config.
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This script derives the following consistent set of include files :
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$RV_ROOT/configs/snapshots/default
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├── common_defines.vh # `defines for testbench or design
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├── defines.h # defines for C/assembly headers
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├── eh2_param.vh # Design parameters
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├── eh2_pdef.vh # Parameter structure
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├── pd_defines.vh # `defines for physical design
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├── perl_configs.pl # Perl %configs hash for scripting
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├── pic_map_auto.h # PIC memory map based on configure size
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└── whisper.json # JSON file for swerv-iss
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### Building a model
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while in a work directory:
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##### 1. Set the RV_ROOT environment variable to the root of the Quasar directory structure.
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Example for bash shell:
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`export RV_ROOT=/path/to/quasar`
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Example for csh or its derivatives:
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`setenv RV_ROOT /path/to/quasar`
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##### 2. Create your specific configuration
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*(Skip if default is sufficient)*
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*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)*. For example, if `mybuild` is the name for the snapshot:
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set BUILD_PATH environment variable:
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`setenv BUILD_PATH snapshots/mybuild`
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`$RV_ROOT/configs/swerv.config [configuration options..] -snapshot=mybuild`
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Snapshots are placed in `$BUILD_PATH` directory
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##### 3. Running a simple Hello World program (verilator)
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`make -f $RV_ROOT/Makefile`
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This command will build a verilator model of Quasar with AXI bus, and
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execute a short sequence of instructions that writes out "HELLO WORLD"
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to the bus.
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The simulation produces output on the screen like:
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`***********************************************************************`
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The simulation generates following files:
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`console.log` contains what the cpu writes to the console address of 0xd0580000.
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`exec.log` shows instruction trace with GPR updates.
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`trace_port.csv` contains a log of the trace port.
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When `debug=1` is provided, a vcd file `sim.vcd` is created and can be browsed by gtkwave or similar waveform viewers.
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You can re-execute simulation using:
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`make -f $RV_ROOT/Makefile verilator`
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The simulation run/build command has following generic form:
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make -f $RV_ROOT/tools/Makefile [<simulator>] [debug=1] [snapshot=mybuild] [target=<target>] [TEST=<test>] [TEST_DIR=<path_to_test_dir>]
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where:
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```
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<simulator> - can be 'verilator' (by default) 'irun' - Cadence xrun, 'vcs' - Synopsys VCS, 'vlog' Mentor Questa
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'riviera'- Aldec Riviera-PRO. if not provided, 'make' cleans work directory, builds verilator executable and runs a test.
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debug=1 - allows VCD generation for verilator and VCS and SHM waves for irun option.
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<target> - predefined CPU configurations 'default' ( by default), 'default_ahb', 'typical_pd', 'high_perf'
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TEST - allows to run a C (<test>.c) or assembly (<test>.s) test, hello_world is run by default
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TEST_DIR - alternative to test source directory testbench/asm or testbench/tests
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<snapshot> - run and build executable model of custom CPU configuration, remember to provide 'snapshot' argument
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for runs on custom configurations.
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CONF_PARAMS - allows to provide -set options to swerv.conf script to alter predefined EL2 targets parameters
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```
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Example:
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make -f $RV_ROOT/Makefile verilator TEST=cmark
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will build and simulate testbench/asm/cmark.c program with verilator
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If you want to compile a test only, you can run:
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make -f $RV_ROOT/Makefile program.hex TEST=<test> [TEST_DIR=/path/to/dir]
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The `$RV_ROOT/testbench/asm` directory contains following tests ready to simulate:
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```
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hello_world - default tes to run, prints Hello World message to screen and console.log
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hello_world_dccm - the same as above, but takes the string from preloaded DCCM.
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hello_world_iccm - the same as hello_world, but loads the test code to ICCM via LSU to DMA bridge and then executes
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it from there. Runs on EL2 with AXI4 buses only.
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cmark - coremark benchmark running with code and data in external memories
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cmark_dccm - the same as above, running data and stack from DCCM (faster)
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cmark_iccm - the same as above with preloaded code to ICCM.
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```
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The `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISCV SW tools are not installed.
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**Note**: The testbench has a simple synthesizable bridge that allows you to load the ICCM via load/store instructions. This is only supported for AXI4 builds.
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