risc-v-tlm/inc/CPU.h

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/*!
\file CPU.h
\brief Main CPU class
\author Màrius Montón
\date August 2018
*/
#ifndef CPU_BASE_H
#define CPU_BASE_H
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include "systemc"
#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "memory.h"
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#include "Execute.h"
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#include "Registers.h"
#include "Log.h"
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#include "Instruction.h"
#include "C_Instruction.h"
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#include "M_Instruction.h"
#include "A_Instruction.h"
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using namespace sc_core;
using namespace sc_dt;
using namespace std;
/**
* @brief ISC_V CPU model
* @param name name of the module
*/
class CPU: sc_module {
public:
tlm_utils::simple_initiator_socket<CPU> instr_bus;
//tlm_utils::simple_initiator_socket<cpu_base> data_bus;
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sc_in<bool> interrupt;
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CPU(sc_module_name name, uint32_t PC);
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~CPU();
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Execute *exec;
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private:
Registers *register_bank;
Performance *perf;
Log *log;
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/**
*
* @brief Process and triggers IRQ if all conditions memory_socket
* @return true if IRQ is triggered, false otherwise
*/
bool cpu_process_IRQ();
/**
* @brief Executes default ISA instruction
* @param inst instruction to execute
* @return true if PC is affected by instruction
*/
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bool process_base_instruction(Instruction &inst);
bool process_c_instruction(Instruction &inst);
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bool process_m_instruction(Instruction &inst);
bool process_a_instruction(Instruction inst);
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void CPU_thread(void);
};
#endif