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Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM

This commit is contained in:
Màrius Montón 2021-11-09 11:18:06 +01:00
parent de1aa4c7a6 73a1047e3e
commit 429a67fbef
2 changed files with 2 additions and 2 deletions
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2
.travis.yml
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@ -13,7 +13,7 @@ before_install:
install: install:
- cd .. - cd ..
- wget http://www.accellera.org/images/downloads/standards/systemc/systemc-2.3.2.tar.gz - wget --no-check-certificate http://www.accellera.org/images/downloads/standards/systemc/systemc-2.3.2.tar.gz
- tar xfvz systemc-2.3.2.tar.gz - tar xfvz systemc-2.3.2.tar.gz
- cd systemc-2.3.2 - cd systemc-2.3.2
- mkdir build && cd build - mkdir build && cd build

2
README.md
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@ -6,7 +6,7 @@
This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2. This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2.
It supports RV32IMAC Instruction set by now. It supports RV32IMAC Instruction set by now.
[![travis](https://travis-ci.org/mariusmm/RISC-V-TLM.svg?branch=master)](https://travis-ci.org/mariusmm/RISC-V-TLM) [![travis](https://api.travis-ci.com/mariusmm/RISC-V-TLM.svg?branch=master)](https://app.travis-ci.com/github/mariusmm/RISC-V-TLM)
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