286dbf07a6
added const keyword to const methods
2021-01-17 15:40:47 +01:00
a019de5eb3
reduce variable scope
2021-01-15 15:51:03 +01:00
2ca86d4688
array init
2021-01-15 15:16:56 +01:00
3bf210556e
fixed initialization array error
2021-01-15 10:27:14 +01:00
9636a53624
Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM
2021-01-15 10:24:31 +01:00
63dfb0f5f1
more warnings
2021-01-15 10:15:08 +01:00
39bb40f189
Fix create directory
2021-01-15 10:14:49 +01:00
f7dbf106cc
trivial changes to increase performance
2021-01-15 09:09:52 +01:00
a713e13705
missing header
2020-12-10 19:34:57 +01:00
a3ad14b670
Replaced std::endl by \n for Log performance
2020-12-10 18:02:42 +01:00
1e9ca5c4e3
documentation
2020-11-12 11:02:26 +01:00
1d271cbb0a
explicit sc_core::wait, typos and newline
2020-07-19 11:18:58 +02:00
d278b1e0a5
Added ecall to asm example files as commented in issue #7
2020-07-17 17:04:05 +02:00
04aa12e42d
fix issue #5
2020-07-10 16:48:29 +02:00
abf47625a1
change fixed array for CSR to unordered map
2020-06-21 00:29:45 +02:00
5b91897244
added likely, unlikely attributes to switch case, could boost perfomance
2020-06-21 00:22:51 +02:00
9feda996e6
Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM
2020-06-20 11:22:39 +02:00
376d3e9e4f
better container class
2020-06-20 11:22:22 +02:00
3cfbdcf6b8
cpp rtti examples
2020-06-11 10:23:35 +02:00
03a228b020
cpp rtti examples
2020-06-11 10:23:20 +02:00
7867d7c592
fixed Makefile to work with cpp files
2020-06-11 09:29:06 +02:00
7ddacbfe1e
C++ example
2020-06-11 09:24:48 +02:00
c33524e726
fixed log condition
2020-06-11 09:23:59 +02:00
5ee634e4b4
Major refactoring!
...
* A_Instruction, C_Instruction and M_Instruction renamed to *_extension
* These files decode and executes extensions
* These classes use a new base clase extension_base
* Execute & Instruction classes heavyly modified:
* Execute now is BASE_ISA and decodes and executes base ISA, Zicsr & Zifencei
* Instruction keeps the instruction being executed, nothing else
* Add memory interface to ISS to clear the code and the structure
* Removed "using namespace " directives, all classes are called using their namespace
* Added proper header to each file
* Added license to all files
2020-06-02 13:08:38 +02:00
9a46e9d0a5
add missing break for case
2020-05-29 16:03:45 +02:00
95b9685ad9
removed creation of class every CPU loop. It should get better performance
2020-05-28 17:18:50 +02:00
4838205aba
FreeRTOS test project
2020-05-28 11:23:43 +02:00
16b86bfe14
add authors and credits
2020-05-26 10:55:12 +02:00
5968a12e5f
typo
2020-05-24 21:04:39 +02:00
7d0620fb9a
add CARRV paper
2020-05-24 21:03:50 +02:00
2aaa83a064
new MSTATUH CSR register
2020-04-14 12:27:09 +02:00
45884cb0bd
new tests
2020-04-11 13:33:12 +02:00
ede34d7768
Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM
2020-04-10 16:43:35 +02:00
5d30416955
Fixed some warnings from coverity
2020-04-10 16:43:22 +02:00
dc5f6aa37b
Makefile for newlib nano and new Trace peripheral explanied
2019-09-25 09:04:44 +02:00
62b8bc4cb2
better docker explanation
2019-09-25 08:15:08 +02:00
1379eca32d
unused option
2019-09-24 11:19:19 +02:00
2e9044a68c
new test using malloc()
2019-09-24 11:18:54 +02:00
d575410a06
if condition clarified
2019-09-24 11:12:47 +02:00
70e9313025
fixed wrong interrupt enable value
2019-09-24 11:03:31 +02:00
5f0da6b208
fixed potential bug on memcpy
2019-09-24 11:02:15 +02:00
7431fc5abb
Fixed Makefile, definitive Makefile using newlib
2019-09-24 11:00:06 +02:00
72ffb2bce3
file renamed
2019-09-20 16:45:38 +02:00
9796130cb5
Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM
2019-09-13 19:11:47 +02:00
b4f355f4fe
updated docker shield
2019-09-13 14:48:18 +02:00
a0907cbbfe
fixed wrong objdump filename
2019-09-13 14:28:43 +02:00
e75a4bfdfd
add missing CSR register MCYcLE and similars
2019-09-13 00:00:59 +02:00
92a450b75e
updated performance with new computer
2019-09-12 11:30:57 +02:00
916ab46907
print out test result at the end of simulation
2019-09-10 12:36:45 +02:00
d63d95f634
fixed bug related DMI access when memory offset != 0
2019-09-10 12:24:46 +02:00
mariusmonton