9636a53624
Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM
2021-01-15 10:24:31 +01:00
f7dbf106cc
trivial changes to increase performance
2021-01-15 09:09:52 +01:00
a713e13705
missing header
2020-12-10 19:34:57 +01:00
1e9ca5c4e3
documentation
2020-11-12 11:02:26 +01:00
abf47625a1
change fixed array for CSR to unordered map
2020-06-21 00:29:45 +02:00
376d3e9e4f
better container class
2020-06-20 11:22:22 +02:00
6ff0da0313
new log file, same performance
2020-06-09 16:37:29 +02:00
5ee634e4b4
Major refactoring!
...
* A_Instruction, C_Instruction and M_Instruction renamed to *_extension
* These files decode and executes extensions
* These classes use a new base clase extension_base
* Execute & Instruction classes heavyly modified:
* Execute now is BASE_ISA and decodes and executes base ISA, Zicsr & Zifencei
* Instruction keeps the instruction being executed, nothing else
* Add memory interface to ISS to clear the code and the structure
* Removed "using namespace " directives, all classes are called using their namespace
* Added proper header to each file
* Added license to all files
2020-06-02 13:08:38 +02:00
95b9685ad9
removed creation of class every CPU loop. It should get better performance
2020-05-28 17:18:50 +02:00
2aaa83a064
new MSTATUH CSR register
2020-04-14 12:27:09 +02:00
5d30416955
Fixed some warnings from coverity
2020-04-10 16:43:22 +02:00
e75a4bfdfd
add missing CSR register MCYcLE and similars
2019-09-13 00:00:59 +02:00
1bb3200eb6
add destructor for clean exit
2019-09-08 11:42:05 +02:00
0415ba3c66
added xterm window for trace output
2019-09-08 11:41:06 +02:00
d42d67b991
DMI access added (if available)
2019-03-28 22:52:36 +01:00
a275e0fa24
better support to IRQs
2019-02-18 13:56:47 +01:00
2c2cf3000b
typos, register definitions
2019-02-11 15:52:48 +01:00
098aebc15d
changed IRQ line to TLM socket
2019-01-22 12:43:05 +01:00
0c25abdb00
Fixed bug
2019-01-22 12:33:32 +01:00
7c263419a8
documentation
2019-01-13 18:39:35 +01:00
a4a1be7386
IRQ implemented
2019-01-13 01:30:49 +01:00
9a7e7abeb0
Better logs
...
Fixed some bugs
2019-01-01 21:11:34 +01:00
5c905cb5ca
better MISA CSR register support
2018-12-12 18:15:44 +01:00
93fe2237b4
better support to hex file
2018-12-12 18:15:21 +01:00
a2a9c95546
Added A Extensions
...
Added SFENCE instruction
2018-12-12 18:14:35 +01:00
1b93e7f569
added time management and cycle counters
2018-11-25 12:07:08 +01:00
0f291016c5
add support to RaiseExecption to all instructions
2018-11-24 23:46:47 +01:00
4114f482d6
Doxygen
2018-11-24 23:46:01 +01:00
c832b2f80f
all tests passed!
2018-11-22 16:42:06 +01:00
b9e26e4dea
first implementation supporting exceptions
2018-11-22 14:38:31 +01:00
6726b59c3c
bug on SLLI
2018-11-22 12:39:16 +01:00
0cd34f9f3b
fixed CSRRS and CSRRC bug
2018-11-22 12:08:16 +01:00
ed7be704f9
implementation of all remaining C extension
2018-11-19 15:56:08 +01:00
a8bdc37c12
all tests passed!
2018-11-14 19:14:57 +01:00
d449ea5502
adding M extensions to simulator
2018-11-12 17:41:17 +01:00
1fcbcf500b
typos 6 minor changes
2018-11-11 11:12:12 +01:00
9d7d84c7f8
bugs!
2018-11-07 18:43:10 +01:00
598699cd54
more bug fixes, still get j zero in func3 test example
2018-10-17 17:42:43 +02:00
374b853117
first version of C.extensions
2018-10-15 17:35:16 +02:00
5ae765b304
Proper initialization of sp register
2018-10-15 17:32:37 +02:00
aa526943b9
Added instructions to pass riscv-tests
2018-10-15 13:51:41 +02:00
f17b3b75d5
new setters to Instruction class
2018-10-10 18:58:08 +02:00
08044ac626
* Instruction: changed name to accessors
...
* CPU: moved huge switch case to a new function
* Execute: changed to use instruction new accessors
2018-10-10 12:08:53 +02:00
70de804983
non-static data intialization removed, moved to constructor
2018-09-27 14:32:40 +02:00
a5773202e1
renamed RISC_V_execute to Execute
2018-09-21 13:05:42 +02:00
afbf317941
updated documentation
2018-09-21 11:23:31 +02:00
21003e2fa9
remove unused SC_THREAD
2018-09-21 09:24:49 +02:00
981b84a5eb
Better register dump
2018-09-20 15:29:22 +02:00
11fae01cba
Changed memory to be addressable to byte instead to word (32bits)
2018-09-20 12:22:13 +02:00
8dcbf09589
Lot of changes:
...
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
1c9bfe8c60
Added Data Memory bus. Implemented LW & SW instructions.
2018-09-17 12:21:26 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
Màrius Montón