Commit Graph

176 Commits

Author SHA1 Message Date
mariusmonton f140f5118f update how to work with assembly files 2019-06-09 21:19:47 +02:00
mariusmonton 1d1c1b0931 added memory map 2019-04-10 11:16:14 +02:00
mariusmonton 471d2c045f Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM 2019-03-28 22:53:53 +01:00
mariusmonton d42d67b991 DMI access added (if available) 2019-03-28 22:52:36 +01:00
Màrius Montón 0a5938a13f
Update issue templates 2019-02-21 13:27:37 +01:00
mariusmonton 24a27f39fe another test, long loop for long tests 2019-02-18 23:28:46 +01:00
mariusmonton 5ad8ced434 better log for CSRRW instruction 2019-02-18 13:57:24 +01:00
mariusmonton 9d89f847a0 better dockerfile style 2019-02-18 13:57:02 +01:00
mariusmonton a275e0fa24 better support to IRQs 2019-02-18 13:56:47 +01:00
mariusmonton a91e590d6d other usage of docker image 2019-02-15 14:30:12 +01:00
mariusmonton e31eae3f9e added command line arguments 2019-02-12 14:08:40 +01:00
mariusmonton 1d4c3ec553 removed unused code 2019-02-12 11:40:25 +01:00
mariusmonton 492cfd61e9 better extension enumeration 2019-02-12 11:39:15 +01:00
mariusmonton 111bf08297 added ISR register to vPortSetupTimer() function 2019-02-11 20:36:16 +01:00
mariusmonton d62892e3dc minor changes, better code 2019-02-11 20:26:23 +01:00
mariusmonton 6f8cc9ded6 updated with FreeRTOS port 2019-02-11 20:16:32 +01:00
mariusmonton 1c50b22c27 FreeRTOS portable files for this simulator 2019-02-11 20:12:30 +01:00
mariusmonton a87743b92d minor changes 2019-02-11 15:54:13 +01:00
mariusmonton 2c93492ab1 enhanced IRQ support 2019-02-11 15:54:02 +01:00
mariusmonton 2c2cf3000b typos, register definitions 2019-02-11 15:52:48 +01:00
mariusmonton 6c0d2708a8 error in docker doc 2019-02-07 22:41:14 +01:00
mariusmonton 23f12f3daf default all: option 2019-02-06 19:14:23 +01:00
mariusmonton c00b1582d9 TOC 2019-02-04 13:16:50 +01:00
mariusmonton 6ea7f7a062 updated docker information 2019-02-03 21:46:38 +01:00
mariusmonton 50147b4762 Added Docker container 2019-02-03 12:05:06 +01:00
mariusmonton a8943a111f enable interrupts writing to mstatus 2019-01-22 19:31:13 +01:00
mariusmonton fa3b178f79 update instruction/second 2019-01-22 18:34:48 +01:00
mariusmonton 4c89c48fb0 removed SP init, moved to CPU module 2019-01-22 18:30:09 +01:00
mariusmonton d6f774eaea Timer module test 2019-01-22 18:29:12 +01:00
mariusmonton e9ef03890f fixed ISR memory alignement 2019-01-22 13:26:41 +01:00
mariusmonton d83a15eec5 change log level 2019-01-22 12:47:54 +01:00
mariusmonton 098aebc15d changed IRQ line to TLM socket 2019-01-22 12:43:05 +01:00
mariusmonton 0c25abdb00 Fixed bug 2019-01-22 12:33:32 +01:00
mariusmonton 7c263419a8 documentation 2019-01-13 18:39:35 +01:00
mariusmonton 64030a7cc3 fixed Makefile errors 2019-01-13 18:20:02 +01:00
mariusmonton 52953bc8de updated with Timer module 2019-01-13 18:12:51 +01:00
mariusmonton 3316575820 updated 2019-01-13 01:36:38 +01:00
mariusmonton d875dc2cd3 comparator value explained 2019-01-13 01:33:28 +01:00
mariusmonton a4a1be7386 IRQ implemented 2019-01-13 01:30:49 +01:00
mariusmonton 6c3b4347a8 link fixed 2019-01-10 15:02:41 +01:00
mariusmonton 2db8092a04 update 2019-01-10 14:58:27 +01:00
mariusmonton f1f98faf13 updates 2019-01-09 23:06:35 +01:00
mariusmonton 532d9f7c85 fixed compiling options 2019-01-09 23:03:08 +01:00
mariusmonton 9a7e7abeb0 Better logs
Fixed some bugs
2019-01-01 21:11:34 +01:00
mariusmonton 5c905cb5ca better MISA CSR register support 2018-12-12 18:15:44 +01:00
mariusmonton 93fe2237b4 better support to hex file 2018-12-12 18:15:21 +01:00
mariusmonton a2a9c95546 Added A Extensions
Added SFENCE instruction
2018-12-12 18:14:35 +01:00
mariusmonton 1b93e7f569 added time management and cycle counters 2018-11-25 12:07:08 +01:00
mariusmonton 81f61c52fc fixed dump function! 2018-11-25 12:05:09 +01:00
mariusmonton 0f291016c5 add support to RaiseExecption to all instructions 2018-11-24 23:46:47 +01:00