10ed1fa653
Changed to template classe to prepare for 64bits version
2022-02-20 11:23:58 +01:00
d1fa3c752e
Register class changed to templated to prepare for rv64 code
2022-02-06 11:41:37 +01:00
fb84f197bf
Added namespace to project
2021-11-29 20:35:26 +01:00
2c4de6a427
Fixed types
2021-11-16 10:27:28 +01:00
a42877ab95
change types from uintX_t to std::uintX_t
2021-11-11 17:10:23 +01:00
d8a20db976
New function to increase PC by 2 (incPCby2) instead of a parameter to incPC function, could be faster code.
2021-11-11 14:52:50 +01:00
1890b62f07
Changed registers to uint32_t.
...
Removed unused initializers.
Add cast from uint to int when necessary.
2021-11-08 09:49:08 +01:00
908b7e965d
Better output, change registers to unsigned int as base. Should be uint32_t?
2021-11-08 09:25:36 +01:00
1777a3bc9a
code clean-up (using clang-tidy)
2021-04-26 00:20:29 +02:00
3b3813bd07
code clean-up (using clang-tidy)
2021-04-25 19:52:12 +02:00
a48e552926
some methods now are const, reference class parameters, other minor changes
2021-01-23 11:44:10 +01:00
2ca86d4688
array init
2021-01-15 15:16:56 +01:00
3bf210556e
fixed initialization array error
2021-01-15 10:27:14 +01:00
f7dbf106cc
trivial changes to increase performance
2021-01-15 09:09:52 +01:00
abf47625a1
change fixed array for CSR to unordered map
2020-06-21 00:29:45 +02:00
5ee634e4b4
Major refactoring!
...
* A_Instruction, C_Instruction and M_Instruction renamed to *_extension
* These files decode and executes extensions
* These classes use a new base clase extension_base
* Execute & Instruction classes heavyly modified:
* Execute now is BASE_ISA and decodes and executes base ISA, Zicsr & Zifencei
* Instruction keeps the instruction being executed, nothing else
* Add memory interface to ISS to clear the code and the structure
* Removed "using namespace " directives, all classes are called using their namespace
* Added proper header to each file
* Added license to all files
2020-06-02 13:08:38 +02:00
2aaa83a064
new MSTATUH CSR register
2020-04-14 12:27:09 +02:00
5d30416955
Fixed some warnings from coverity
2020-04-10 16:43:22 +02:00
e75a4bfdfd
add missing CSR register MCYcLE and similars
2019-09-13 00:00:59 +02:00
2c2cf3000b
typos, register definitions
2019-02-11 15:52:48 +01:00
a4a1be7386
IRQ implemented
2019-01-13 01:30:49 +01:00
5c905cb5ca
better MISA CSR register support
2018-12-12 18:15:44 +01:00
1b93e7f569
added time management and cycle counters
2018-11-25 12:07:08 +01:00
b9e26e4dea
first implementation supporting exceptions
2018-11-22 14:38:31 +01:00
6726b59c3c
bug on SLLI
2018-11-22 12:39:16 +01:00
0cd34f9f3b
fixed CSRRS and CSRRC bug
2018-11-22 12:08:16 +01:00
5ae765b304
Proper initialization of sp register
2018-10-15 17:32:37 +02:00
981b84a5eb
Better register dump
2018-09-20 15:29:22 +02:00
8dcbf09589
Lot of changes:
...
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
Màrius Montón