6b21b1bfee
Remove #include from headers and move to cpp file.
2022-09-19 14:43:44 +02:00
56b00aecd8
Helper parameter for test-suite
2022-09-14 20:01:36 +02:00
2615ccc8f8
Some specializations, removed lot of useless casts.
2022-07-22 13:28:36 +02:00
fc85c603d4
Two instances of CPU (RV32, RV64). Need to implement RV64 specific instructions.
2022-07-21 15:33:23 +02:00
10ed1fa653
Changed to template classe to prepare for 64bits version
2022-02-20 11:23:58 +01:00
d1fa3c752e
Register class changed to templated to prepare for rv64 code
2022-02-06 11:41:37 +01:00
fb84f197bf
Added namespace to project
2021-11-29 20:35:26 +01:00
724cf258ce
merge with log branch. New log mechanism
2021-11-25 13:01:23 +01:00
e6bf4e30a4
Use spdlog library as logger.
2021-11-25 12:11:18 +01:00
61be24e608
changed pointer by reference
2021-11-16 10:26:42 +01:00
a42877ab95
change types from uintX_t to std::uintX_t
2021-11-11 17:10:23 +01:00
c9bab2ae27
Remove SC_MODULE macros, other trivial code clean-up
2021-06-30 15:37:18 +02:00
3b3813bd07
code clean-up (using clang-tidy)
2021-04-25 19:52:12 +02:00
4c60d6ae75
Prepare for debug
2021-02-21 13:48:41 +01:00
6ff0da0313
new log file, same performance
2020-06-09 16:37:29 +02:00
5ee634e4b4
Major refactoring!
...
* A_Instruction, C_Instruction and M_Instruction renamed to *_extension
* These files decode and executes extensions
* These classes use a new base clase extension_base
* Execute & Instruction classes heavyly modified:
* Execute now is BASE_ISA and decodes and executes base ISA, Zicsr & Zifencei
* Instruction keeps the instruction being executed, nothing else
* Add memory interface to ISS to clear the code and the structure
* Removed "using namespace " directives, all classes are called using their namespace
* Added proper header to each file
* Added license to all files
2020-06-02 13:08:38 +02:00
95b9685ad9
removed creation of class every CPU loop. It should get better performance
2020-05-28 17:18:50 +02:00
d42d67b991
DMI access added (if available)
2019-03-28 22:52:36 +01:00
a275e0fa24
better support to IRQs
2019-02-18 13:56:47 +01:00
2c2cf3000b
typos, register definitions
2019-02-11 15:52:48 +01:00
098aebc15d
changed IRQ line to TLM socket
2019-01-22 12:43:05 +01:00
a4a1be7386
IRQ implemented
2019-01-13 01:30:49 +01:00
a2a9c95546
Added A Extensions
...
Added SFENCE instruction
2018-12-12 18:14:35 +01:00
d449ea5502
adding M extensions to simulator
2018-11-12 17:41:17 +01:00
aa526943b9
Added instructions to pass riscv-tests
2018-10-15 13:51:41 +02:00
08044ac626
* Instruction: changed name to accessors
...
* CPU: moved huge switch case to a new function
* Execute: changed to use instruction new accessors
2018-10-10 12:08:53 +02:00
a5773202e1
renamed RISC_V_execute to Execute
2018-09-21 13:05:42 +02:00
8dcbf09589
Lot of changes:
...
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
1c9bfe8c60
Added Data Memory bus. Implemented LW & SW instructions.
2018-09-17 12:21:26 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
Màrius Montón