f029d365be
Unaligned jalr raise exception, ecall raise exception
2021-09-01 09:11:45 +02:00
06748d99bc
New options to use with riscv-arch-test suite
2021-07-04 22:48:10 +02:00
56c5203899
Use real addresses in memory, extend memory size fo 0xFFFFFFFF
2021-07-04 22:47:47 +02:00
34a8f66035
Simplified extension check
2021-07-04 22:46:41 +02:00
5f47a8a906
Flush log file to save all data to disk before close simulator.
2021-06-30 17:28:10 +02:00
c9bab2ae27
Remove SC_MODULE macros, other trivial code clean-up
2021-06-30 15:37:18 +02:00
40c9d678ef
code clean-up (using clang-tidy)
2021-04-26 00:38:47 +02:00
08bb222df9
code clean-up (using clang-tidy)
2021-04-26 00:36:46 +02:00
1777a3bc9a
code clean-up (using clang-tidy)
2021-04-26 00:20:29 +02:00
3b3813bd07
code clean-up (using clang-tidy)
2021-04-25 19:52:12 +02:00
295e86a324
fixed (silly way) unused ret value
2021-02-21 20:54:15 +01:00
bfb537e0d5
deprecated constructor
2021-02-21 20:53:39 +01:00
e340264670
fixed some bug, removed cout output
2021-02-21 19:32:52 +01:00
0e80259674
call to sc_module constructor
2021-02-21 16:17:57 +01:00
ea04c6ac37
fixe enum name
2021-02-21 14:04:24 +01:00
512e701f22
removed unused constructor parameters
2021-02-21 14:04:11 +01:00
49103e5591
Prepare for debug
2021-02-21 13:49:05 +01:00
4c60d6ae75
Prepare for debug
2021-02-21 13:48:41 +01:00
5927dade4d
check memory boundaries
2021-02-21 13:47:06 +01:00
9b7b5635d2
removed CPU64 files (unused)
2021-02-02 19:56:14 +01:00
db682f6055
removed typedef, use default_time instead of fixed time
2021-02-02 19:53:18 +01:00
b3b00ac7f3
more performance metrics output
2021-02-01 11:24:53 +01:00
1d1b6de616
reduce scope variables
2021-01-31 12:09:15 +01:00
622da9872a
added performace information for data memory accesses
2021-01-31 12:00:25 +01:00
337e267218
remove unused trace output from destructor
2021-01-31 11:59:56 +01:00
86b98209ce
exit cleanup, now closes xterm window, etc.
2021-01-31 11:38:57 +01:00
a48e552926
some methods now are const, reference class parameters, other minor changes
2021-01-23 11:44:10 +01:00
cb63c65d7f
Implemented C_EBREAK instruction
2021-01-18 09:14:54 +01:00
286dbf07a6
added const keyword to const methods
2021-01-17 15:40:47 +01:00
a019de5eb3
reduce variable scope
2021-01-15 15:51:03 +01:00
f7dbf106cc
trivial changes to increase performance
2021-01-15 09:09:52 +01:00
a3ad14b670
Replaced std::endl by \n for Log performance
2020-12-10 18:02:42 +01:00
1d271cbb0a
explicit sc_core::wait, typos and newline
2020-07-19 11:18:58 +02:00
abf47625a1
change fixed array for CSR to unordered map
2020-06-21 00:29:45 +02:00
5b91897244
added likely, unlikely attributes to switch case, could boost perfomance
2020-06-21 00:22:51 +02:00
c33524e726
fixed log condition
2020-06-11 09:23:59 +02:00
5ee634e4b4
Major refactoring!
...
* A_Instruction, C_Instruction and M_Instruction renamed to *_extension
* These files decode and executes extensions
* These classes use a new base clase extension_base
* Execute & Instruction classes heavyly modified:
* Execute now is BASE_ISA and decodes and executes base ISA, Zicsr & Zifencei
* Instruction keeps the instruction being executed, nothing else
* Add memory interface to ISS to clear the code and the structure
* Removed "using namespace " directives, all classes are called using their namespace
* Added proper header to each file
* Added license to all files
2020-06-02 13:08:38 +02:00
9a46e9d0a5
add missing break for case
2020-05-29 16:03:45 +02:00
95b9685ad9
removed creation of class every CPU loop. It should get better performance
2020-05-28 17:18:50 +02:00
ede34d7768
Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM
2020-04-10 16:43:35 +02:00
5d30416955
Fixed some warnings from coverity
2020-04-10 16:43:22 +02:00
d575410a06
if condition clarified
2019-09-24 11:12:47 +02:00
5f0da6b208
fixed potential bug on memcpy
2019-09-24 11:02:15 +02:00
e75a4bfdfd
add missing CSR register MCYcLE and similars
2019-09-13 00:00:59 +02:00
916ab46907
print out test result at the end of simulation
2019-09-10 12:36:45 +02:00
d63d95f634
fixed bug related DMI access when memory offset != 0
2019-09-10 12:24:46 +02:00
1bb3200eb6
add destructor for clean exit
2019-09-08 11:42:05 +02:00
1babf6cb88
added sc_stop at the end of the simulation to call destructors
2019-09-08 11:41:30 +02:00
0415ba3c66
added xterm window for trace output
2019-09-08 11:41:06 +02:00
d42d67b991
DMI access added (if available)
2019-03-28 22:52:36 +01:00
Màrius Montón