2025-05-11 16:27:43 +08:00
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create_project -force my_project
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set_property SOURCE_MGMT_MODE None [current_project]
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set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
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set_property PART xc7k480tffg1156-2L [current_project]
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2025-05-10 23:24:56 +08:00
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# # 生成IP核（以AXI UART Lite为例）
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# create_ip -name axi_uartlite -vendor xilinx.com -library ip -version 2.0 -module_name uart_inst
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# # 配置IP参数
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# set_property -dict [list \
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# CONFIG.C_BAUDRATE {115200} \
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# CONFIG.C_S_AXI_ACLK_FREQ_HZ {100000000} \
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# CONFIG.C_DATA_BITS {8} \
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# CONFIG.C_USE_PARITY {0} \
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# ] [get_ips uart_inst]
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2025-05-11 16:27:43 +08:00
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create_ip -name axi_interconnect -vendor xilinx.com -library ip -version 1.7 -module_name axi_interconnect_0
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generate_target -force all [get_ips axi_interconnect_0]
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synth_ip [get_ips axi_interconnect_0]
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2025-05-10 23:24:56 +08:00
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# add_file ../uart_inst.xci
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2025-05-11 16:27:43 +08:00
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# import_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
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# import_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
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# import_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
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import_ip ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci
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# upgrade_ip [get_ips Top_axi_interconnect_0_0]
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# # set_property GENERATE_SYNTH_CHECKPOINT true Top_axi_interconnect_0_0
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# generate_target -force all [get_ips Top_axi_interconnect_0_0]
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# synth_ip [get_ips Top_axi_interconnect_0_0]
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# import_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
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# import_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
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# import_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci
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# import_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
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# import_ip ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
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# import_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
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# import_ip ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci
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# generate_target all [get_ips Top_axi_bram_ctrl_0_0]
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# generate_target all [get_ips Top_util_vector_logic_1_3]
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# generate_target all [get_ips Top_xlconstant_2_0]
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# generate_target all [get_ips Top_axi_interconnect_0_0]
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# generate_target all [get_ips Top_util_vector_logic_1_4]
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# generate_target all [get_ips Top_blk_mem_gen_0_0]
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# generate_target all [get_ips Top_xbar_0]
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# generate_target all [get_ips Top_mig_7series_1_0]
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# generate_target all [get_ips Top_xdma_1_0]
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# generate_target all [get_ips Top_util_ds_buf_0_0]
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# generate_target all [get_ips Top_xlconstant_0_0]
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# synth_ip [get_ips Top_axi_bram_ctrl_0_0]
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# synth_ip [get_ips Top_util_vector_logic_1_3]
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# synth_ip [get_ips Top_xlconstant_2_0]
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# synth_ip [get_ips Top_axi_interconnect_0_0]
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# synth_ip [get_ips Top_util_vector_logic_1_4]
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# synth_ip [get_ips Top_blk_mem_gen_0_0]
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# synth_ip [get_ips Top_xbar_0]
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# synth_ip [get_ips Top_mig_7series_1_0]
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# synth_ip [get_ips Top_xdma_1_0]
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# synth_ip [get_ips Top_util_ds_buf_0_0]
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# synth_ip [get_ips Top_xlconstant_0_0]
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# add_file ../sources/Top_wrapper.v
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# add_file ../sources/Top.bd
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# add_file -fileset constrs_1 ../normal.xdc
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# set_property TOP Top_wrapper [current_fileset]
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# set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1]
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# close_project
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# open_project my_project
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# # Synthesis
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2025-05-11 00:07:51 +08:00
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2025-05-11 16:27:43 +08:00
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# # PRESYNTH
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# # set_property DESIGN_MODE GateLvl [current_fileset]
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# reset_run synth_1
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# launch_runs synth_1
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# wait_on_run synth_1
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# #report_property [get_runs synth_1]
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# if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }
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2025-05-11 00:07:51 +08:00
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2025-05-11 16:27:43 +08:00
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# # Place and Route
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2025-05-11 00:07:51 +08:00
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2025-05-11 16:27:43 +08:00
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# reset_run impl_1
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# launch_runs impl_1
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# wait_on_run impl_1
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# #report_property [get_runs impl_1]
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# if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }
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2025-05-11 00:07:51 +08:00
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2025-05-11 16:27:43 +08:00
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# # Bitstream generation
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2025-05-11 00:07:51 +08:00
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2025-05-11 16:27:43 +08:00
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# open_run impl_1
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# # write_bitstream -force xdma480t
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# # write_debug_probes -force -quiet xdma480t.ltx
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2025-05-10 23:24:56 +08:00
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2025-05-11 16:27:43 +08:00
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# close_project
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2025-05-10 23:24:56 +08:00
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