Update nitefury_pcie_xdma_ddr.

nitefury_pcie_xdma_ddr/.gitignore

@@ -1 +1 @@
-nitefury_xdma_ddr
+nitefury_xdma_ddr_github

nitefury_pcie_xdma_ddr/project/o.tcl

@@ -15,11 +15,29 @@ create_project my_project ./my_project -part xc7k480tffg1156-2L -force
 
 # add_file ../uart_inst.xci
 add_file  ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
+add_file  ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
+
+generate_target all [get_ips Top_axi_bram_ctrl_0_0]
+generate_target all [get_ips Top_xlconstant_2_0]
+
+
+
+# add_file ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
+# add_file ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
+# add_file ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
+# add_file ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci
+# add_file ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
+# add_file ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
+# add_file ../sources/ip/Top_xbar_0/Top_xbar_0.xci
+# add_file ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
+# add_file ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
+# add_file ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
+# add_file ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci
+
 
 
-# 生成IP输出文件（RTL、约束、网表等）
-generate_target -force all [get_ips Top_axi_bram_ctrl_0_0]
 synth_ip [get_ips Top_axi_bram_ctrl_0_0]
+synth_ip [get_ips Top_xlconstant_2_0]
 
 # write_ip_tcl -help
 # write_ip_tcl -force -verbose [get_ips uart_inst] ./uart_inst.tcl

nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci

@@ -46,7 +46,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci

@@ -46,7 +46,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci

@@ -46,7 +46,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci

@@ -44,7 +44,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci

@@ -44,7 +44,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci

@@ -44,7 +44,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci

@@ -44,7 +44,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci

@@ -44,7 +44,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_us_0/Top_auto_us_0.xci

@@ -44,7 +44,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci

@@ -47,7 +47,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci

@@ -328,7 +328,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci

@@ -162,7 +162,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci

@@ -1167,7 +1167,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci

@@ -33,7 +33,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci

@@ -21,7 +21,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci

@@ -21,7 +21,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci

@@ -1244,7 +1244,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci

@@ -1279,7 +1279,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci

@@ -20,7 +20,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],

nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci

@@ -20,7 +20,7 @@
         "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k480ti" } ],
+        "DEVICE": [ { "value": "xc7k480t" } ],
         "PACKAGE": [ { "value": "ffg1156" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],