Luke Wren
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185194973f
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Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
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2022-08-06 23:02:08 +01:00 |
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Luke Wren
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81aec325bb
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ecall from U-mode has a different mcause value than ecall from M-mode
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2022-05-28 12:07:29 +01:00 |
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Luke Wren
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210dbeae64
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
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Luke Wren
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43e0b1d16a
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Implement Zbkb (untested)
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2022-05-06 17:36:25 +01:00 |
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Luke Wren
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28b53ef7b5
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Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
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2021-12-18 00:35:13 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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a988adfec8
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Add RISC-V opcodes and memory operation codes for atomics
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2021-12-04 11:16:24 +00:00 |
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Luke Wren
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58c20a39d0
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First pass at implementing bitmanip. Breaks CXXRTL. Ooop
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2021-11-25 23:30:35 +00:00 |
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Luke Wren
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1b252d4bda
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Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
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2021-05-23 11:59:46 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |