41eeb90c7d
Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
2021-11-26 01:29:47 +00:00
998f3fdeb7
Clean up silly mistakes
2021-11-26 00:55:57 +00:00
58c20a39d0
First pass at implementing bitmanip. Breaks CXXRTL. Ooop
2021-11-25 23:30:35 +00:00
ed6b6a3660
Cleanup order of declaration/use of a couple of wires
2021-11-25 15:16:59 +00:00
2aac3d4f91
Add attempt at CPU backend diagram
2021-11-23 22:14:55 +00:00
e352715fdf
Fix IO decode in openocd/tb.cpp
2021-11-23 22:12:51 +00:00
49462a8642
Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh
2021-11-23 22:11:50 +00:00
e05e9a4109
Add default_nettype none at top of every file, and default_nettype wire at bottom
2021-11-23 22:10:39 +00:00
0b9b706e81
Safer logic for load/store blocked by preceding WFI
2021-11-23 22:01:14 +00:00
4d14203586
Update riscv-tests fork for crash loop debug test
2021-11-23 21:58:39 +00:00
60f364e561
Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker
2021-11-21 15:55:52 +00:00
ba9a7b4a03
Fix broken link in readme
2021-11-21 14:58:07 +00:00
c1f17b0b23
Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
2021-11-06 09:59:27 +00:00
cc6a6c09ba
Vaguely implement wfi
2021-11-05 18:48:42 +00:00
375a6d60b7
Correct mnemonic when logging unsigned sltiu instruction
2021-10-08 12:02:37 +01:00
cfe16caf41
Remove some old todos
2021-09-05 22:20:40 +01:00
e9fccffca0
Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
2021-09-05 04:45:38 +01:00
65bfca5fdf
Fix latent bug with asynchronous debug entry during stalled load/store address phase
2021-09-04 07:49:29 +01:00
d03a82a826
Add instruction fetch faults
2021-09-04 02:57:39 +01:00
9173bcf585
Experimentally add SPI XIP to SoC (breaks FTDI UART on iCEBreaker -- need to move UART to a PMOD to avoid IO conflict)
2021-08-21 17:04:15 +01:00
e16ae06cb5
Clean up timer
2021-08-21 17:03:32 +01:00
9dd091b7b5
Doh typo
2021-08-21 09:06:20 +01:00
b99e5b8a67
Convert timer to serial for smaller area. Rather untested
2021-08-20 22:27:15 +01:00
4aba165166
First pass at a 64-bit system timer
2021-08-20 21:49:05 +01:00
924967ee72
Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k
2021-07-25 13:41:04 +01:00
5976a8a9b7
Add activity LED to iCEBreaker
2021-07-25 13:13:41 +01:00
91edd62ea1
Bump libfpga for FIFO coding style tweak
2021-07-24 22:06:57 +01:00
8263ee3a5d
Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception
2021-07-24 15:31:33 +01:00
6fcc74a043
Add some instructions to Readme
2021-07-24 11:53:08 +01:00
70a44d9681
Small code cleanup
2021-07-24 10:08:27 +01:00
2b1dee4bcc
Fix broken submodule path
2021-07-24 09:55:06 +01:00
155d3ba554
Tie off 1 or 2 LSBs of DPC depending on IALIGN
2021-07-23 23:09:03 +01:00
115cb2c50f
Tweaks to example soc configuration
2021-07-23 23:08:23 +01:00
279e4b4f29
Implement mstatush as hardwired-0, as required by priv-1.12
2021-07-23 21:52:01 +01:00
2ae30183aa
Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
2021-07-23 18:32:47 +01:00
8ceae7e9e6
Start hacking on ECP5 JTAG DTM
2021-07-23 00:36:55 +01:00
41477ce479
Extract DTM bus/control logic from the JTAG-related parts
2021-07-22 19:26:25 +01:00
b0d11c0ab7
Add RISC-V debug tests
2021-07-22 17:50:04 +01:00
c14960ee1b
Add mtime/mtimecmp to openocd testbench
2021-07-22 17:31:26 +01:00
5d2a562f65
Just use read_verilog; write_cxxrtl when building tb_cxxrtl
2021-07-22 17:30:30 +01:00
8cdde82248
Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends
2021-07-20 00:13:26 +01:00
7d24f42da9
Oops, properly fix platform IRQ mcause numbers
2021-07-19 09:32:59 +01:00
65fb62901e
Mask off trap entry assertion from IRQs when in debug mode. Because the IRQ is level-sensitive, this caused trap entry to be held asserted when an IRQ fired in debug mode. This was exposed by the last bug fix -- it is only seen now that MIE+MPIE shuffling is correctly disabled in debug mode.
2021-07-19 00:19:56 +01:00
70443fa557
Disable shifting of MIE/MPIE stack when in or entering debug mode
2021-07-18 21:14:11 +01:00
e4b0d999cb
Minor doc updates
2021-07-18 20:45:08 +01:00
d30fc46f5b
Fix IRQ mcause not being set correctly when vectoring is disabled
2021-07-18 20:44:39 +01:00
c56c75e14b
More dicking with yosys cmd for tb_cxxrtl;
...
Removing the prep pass as suggested leads to invalid VCD net names.
Adding a opt_clean (+ prerequisites) fixes that.
Adding splitnets -driver afterward wins back the performance lost by
that last addition. Can you tell I don't know what I'm doing
2021-07-18 16:46:00 +01:00
12bf9bb570
Make CXXRTL testbench ~25% faster
2021-07-18 16:04:19 +01:00
2618ae0c07
Double-step() after clock posedge to workaround CXXRTL port propagation issue
2021-07-18 16:03:53 +01:00
ce5cc1f150
oops, bounds checking on free-running tb_cxxrtl
2021-07-18 15:20:25 +01:00
Luke Wren
Luke Wren
Richard-Gordon
Vadzim Dambrouski
whitequark