a861a110c1
Update to the latest riscv-arch-test. This uses the new test
...
framework -- scripts are a little janky for now.
Note there is one test failure (cebreak-01) -- analysis shows
this is due to the reference vector expecting mtval to be set
informatively, whereas our implementation (legally) ties it
to zero. Non-mtval-related signature for that test is correct
so I'm saying this is fine.
2023-03-31 01:39:48 +01:00
d29bb13c4a
Replace SSH submodule URLs with HTTPS, oops
2021-11-28 22:26:29 +00:00
47ce2cc8ec
Add embench submodule, with configs for hazard3
2021-11-28 00:01:18 +00:00
2b1dee4bcc
Fix broken submodule path
2021-07-24 09:55:06 +01:00
b0d11c0ab7
Add RISC-V debug tests
2021-07-22 17:50:04 +01:00
f4952ab66d
Add simple example SoC, hangs nextpnr for some reason!
2021-07-13 03:40:06 +01:00
2330b84b73
Use .f for riscv-formal tb dependencies, small reshuffling of directories
2021-05-30 09:44:57 +01:00
90acfdcbe8
Organise test directory into formal and sim
2021-05-23 07:42:35 +01:00
692abbad8b
Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
2021-05-22 07:55:13 +01:00
6dad4e20bb
Import from hazard5 9743a1b
2021-05-21 02:34:16 +01:00
Luke Wren
Vadzim Dambrouski