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128 Commits

Author SHA1 Message Date
Luke Wren 2e3d69e98f Forgot to add expected output for preemption test 2022-08-07 22:08:50 +01:00
Luke Wren 5e72ec8941 Fix a couple of bugs in preemption priority update, add simple IRQ preemption test 2022-08-07 22:04:42 +01:00
Luke Wren 15cb21ae43 First pass at implementing the new IRQ controls. Works well enough that the old tests pass :) 2022-08-07 20:51:12 +01:00
Luke Wren 185194973f Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains 2022-08-06 23:02:08 +01:00
Luke Wren 9787c604ad Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm) 2022-07-30 17:31:53 +01:00
Luke Wren ee7d8e1947 Bump embench for script fixes/improvements 2022-07-07 18:29:37 +01:00
Luke Wren 91be98f2da Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench) 2022-07-06 23:53:11 +01:00
Luke Wren 5a39d8b7e7 Track minstret and mcycle separately now that the model is cycle-accurate 2022-07-06 13:50:13 +01:00
Luke Wren 5dfe5cb62b Update rvpy to match current fastest config: stage 2 mul, single BTB entry on backward branches 2022-07-06 13:49:51 +01:00
Luke Wren b7d9defcf2 Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3 2022-07-05 03:37:19 +01:00
Luke Wren 27793b25a1 Rebase riscv-tests against upstream, and pick up new semihosting file io test 2022-07-04 00:45:20 +01:00
Luke Wren e44d2e6f9e Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed 2022-07-03 23:34:12 +01:00
Luke Wren 9e15cd3485 Add standalone SBA-to-AHB shim, and make SBA off by default in the DM 2022-07-03 15:30:33 +01:00
Luke Wren d5cd3e0681 Add SBA patch-through to 1-core wrapper. 
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
 2022-07-03 15:17:44 +01:00
Luke Wren 51bc26f8ac First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough. 2022-07-03 00:25:47 +01:00
Luke Wren 8ef9d77be8 Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations. 
Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)
 2022-06-25 13:11:40 +01:00
Luke Wren d9389fb23e Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data. 2022-06-16 01:42:28 +01:00
Luke Wren d31b1708db Make rvpy cycle-accurate enough to get the correct Dhrystone score 2022-06-09 01:34:37 +01:00
Luke Wren 02b303b385 Remove stray old expected output file from sw_testcases dir 2022-06-03 17:20:49 +01:00
Luke Wren e2c9901701 Update readme for runtests 2022-05-30 01:12:16 +01:00
Luke Wren 2cfe6aa90e Add test to check MPRV/MPP behaviour when executing an MRET 2022-05-29 19:51:19 +01:00
Luke Wren f96a0ffb75 Add test for MPRV vs PMP 2022-05-29 19:06:04 +01:00
Luke Wren 71eff7649d Add PMP U-mode read/write permission test 2022-05-29 18:42:44 +01:00
Luke Wren c8afcdbb8f Extend umode_wfi test to check U-mode WFI doesn't stall the processor if TW=0 or PMP X check fails 2022-05-29 17:42:15 +01:00
Luke Wren 460fa0bb4a Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented. 2022-05-28 17:22:28 +01:00
Luke Wren 66965ac073 Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted 2022-05-28 15:36:21 +01:00
Luke Wren 4090f4eb24 Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat 2022-05-28 15:01:27 +01:00
Luke Wren 9e2f5df00a Add testbench flag to propagate CPU return code to testbench return 2022-05-28 15:00:28 +01:00
Luke Wren 81aec325bb ecall from U-mode has a different mcause value than ecall from M-mode 2022-05-28 12:07:29 +01:00
Luke Wren 632c61daba Rebase debug tests, pick up two new tests (both pass) 2022-05-28 11:34:41 +01:00
Luke Wren f2876eb51f Fix bad mepc reported after branching to a branch in a no-X address range 2022-05-27 22:47:04 +01:00
Luke Wren b655148148 Bump riscv-tests for better PMP disable fix 2022-05-27 21:36:54 +01:00
Luke Wren e208652ad7 Fix misa value in csr_id test 2022-05-26 00:48:12 +01:00
Luke Wren d7787942e9 Add two new tests to debug test list. Remainder are still non-applicable 2022-05-26 00:47:08 +01:00
Luke Wren a17b941e38 Add U bit to misa, and fix some broken debug tests (no hazard3 bugs) 2022-05-25 23:46:23 +01:00
Luke Wren 37f7588bad Fix hazard3 reset vector check value in debug tests 2022-05-25 21:45:36 +01:00
Luke Wren 5be8835365 Add missing output to pmp_write_and_lock test 2022-05-25 15:34:28 +01:00
Luke Wren 399dcf2cb9 Add test for U-mode X permissions 2022-05-25 13:47:16 +01:00
Luke Wren 7340765699 Add simple test to read, write and lock PMP registers 2022-05-25 02:05:24 +01:00
Luke Wren 456810b09e Make vcd generation optional in runtests 2022-05-24 22:56:13 +01:00
Luke Wren 64d9f4a111 Add tests for execution of mret and wfi in U mode 2022-05-24 22:14:20 +01:00
Luke Wren 20f06c4a02 Build tb with 4 PMP regions by default 2022-05-24 20:06:57 +01:00
Luke Wren 7cfc976ef2 Set U RWX permission on all of memory in the U CSR readability test 2022-05-24 19:58:12 +01:00
Luke Wren cfed35b3da Fix the stupid printf warning on x86-64 as well as arm64 2022-05-24 18:22:25 +01:00
Luke Wren f033cde874 Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp 2022-05-24 17:30:24 +01:00
Luke Wren ba81b533d2 Build core with U mode support for tb 2022-05-24 16:44:22 +01:00
Luke Wren 0199f48087 Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented 2022-05-24 16:44:03 +01:00
Luke Wren 4ba3f7ceb9 Fix format warning in tb.cpp on arm64 2022-05-24 16:17:54 +01:00
Luke Wren ef35dc859d Add zicsr to march in makefiles 2022-05-24 16:17:54 +01:00
Luke Wren 07d4b23a9a Add option to pass test list to runtests 2022-05-24 16:17:54 +01:00