8e7ffb040c
Comment typo
2022-12-17 11:39:47 +00:00
52e665fb45
Remove unnecessary clear of sleep flags on bus error (which had a
...
TODO asking if it should be removed) and add some more properties
in its place.
2022-11-05 18:50:41 +00:00
05cb6e7ee8
Rename confusingly named power control signal for allowing clock gate to shut during WFI/block sleep.
2022-11-05 18:26:56 +00:00
c81666177e
Remove FIXME about considering concurrent load/store and debug entry
...
in calculating the privilege of load/stores. This is safe because it
is only the *current* debug mode state which affects load/stores,
and some new properties have been added to ensure load/stores can
not be in aphase at the point debug mode is entered/exited (which
is achieved by delaying the trap). Therefore there is no way for
debug entry to inadvertently boost the privilege of an executing
U-mode load/store.
Also rename a confusingly-named signal for an unsquashable bus
transfer in stage 2 that delays IRQ entry.
2022-11-05 18:19:14 +00:00
97bf2d06f6
Hold off first instruction fetch until pwrup_ack is first seen high
2022-11-05 14:58:47 +00:00
dff278ea05
Increase DTM idle cycle hint to 8 cycles -- see #6
2022-10-19 21:11:18 +01:00
1953773ca5
Don't gate exception into D-mode CSR write, as a valid CSR instruction
...
writing to a valid CSR in D-mode is guaranteed not to raise any exception
(particularly the external data0 CSR is of interest)
2022-10-10 22:15:56 +01:00
ae4ddf7001
Clean up the old/unused W_COUNTER parameter, and use a cleaner tie-off style for the counter CSRs
2022-10-10 16:33:31 +01:00
f771a1294d
Alias DPC to the real program counter, small savings overall
2022-10-10 00:28:42 +01:00
aa438fc37c
Remove op_b (rs2) register from muldiv_seq for modest LUT/FF savings
2022-10-08 18:22:16 +01:00
d3667769d2
Arrange for address buses to be 0 when processor is held in reset
2022-10-08 16:50:58 +01:00
633a07fef9
Tidy up priority tie-offs in irq_ctrl
2022-10-08 16:25:05 +01:00
5e7bf0d604
Don't reset register file by default
2022-10-08 16:24:28 +01:00
f329d30713
Typo in docs introduction
2022-10-08 15:10:45 +01:00
489480dc80
Revise default config values, and update docs with new values
2022-10-08 08:43:25 +01:00
0b18fae32e
Fix swapped MHARTID/MCONFIGPTR values in tb configs
2022-10-08 08:42:50 +01:00
874cb20910
Add config headers to tb_cxxrtl instead of using defparams in Makefile
2022-10-08 08:09:26 +01:00
8721bd3deb
Add RISC-V timer to example soc, and tweak ULX3S config
2022-10-07 03:11:36 +01:00
a18c3018e1
Bump riscv-formal to head of hazard3 branch, not sure what happened there
2022-10-07 01:35:10 +01:00
bf1bca2ca5
Remove FPGA synth netlist checked in by mistake
2022-10-06 16:00:27 +01:00
1036d15467
Clean up duplicate declaration of external_irq_pending in hazard3_irq_ctrl
2022-10-06 15:59:54 +01:00
4b94c9a2d4
Document new configuration for IRQ and PMPM extensions
2022-10-06 00:19:13 +01:00
e6aaf4b801
Avoid IRQ to bus through-path when custom IRQs are disabled
2022-10-06 00:16:10 +01:00
c55d3f0d0b
Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.
2022-10-05 23:53:04 +01:00
d1d70efa60
Fix some width issues introduced by last commit
2022-10-05 22:19:02 +01:00
6f8b75c041
Make IRQ vectors right-sized. CXXRTL was spending > 1/3rd of its time in the CSR update.
2022-10-05 22:11:53 +01:00
0915cc2834
Doh
2022-09-08 15:11:24 +01:00
f48177c644
Tie off debug LEDs in ULX3S top level
2022-09-05 00:37:44 +01:00
9eb8590858
Add generate to avoid elaborating internals of PMP/triggers with 0 PMP regions or triggers.
2022-09-05 00:36:41 +01:00
18c64bd633
Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression
2022-09-04 23:56:14 +01:00
787a7ec372
Fix bad preprocessor conditional in ECP5 JTAG DTM
2022-09-04 23:48:58 +01:00
c594ec42e9
Change style of IRQ register tie-offs as Yosys was not able to trim them for iCE40 synthesis.
2022-09-04 23:43:24 +01:00
3ae843034d
Example soc: connect up power signals and always-on clock. Set more parameters explicitly.
2022-09-04 23:42:48 +01:00
624d39669d
Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.
2022-08-29 19:20:09 +01:00
1c2249dbef
Typo
2022-08-29 16:25:12 +01:00
6abd93eb49
Oops, masked the wakeup-on-halt request path when I masked IRQs on WFI state.
2022-08-29 16:15:19 +01:00
099f0467fb
Clean up remnants of the 'wfi_is_nop' thing that seemed like a good idea at the time
2022-08-29 15:56:57 +01:00
da4097ecd8
Delay pwrup_req->pwrup_ack in tb
2022-08-29 14:55:11 +01:00
954bae5cf1
Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
2022-08-29 14:52:01 +01:00
b352d3878d
Update docs for new power control extension
2022-08-28 19:54:55 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
ce93c45e69
Add docs section for custom extensions
2022-08-28 15:50:26 +01:00
bf38d93d33
Remove references to AHB-Lite, describe buses as (a subset of) AHB5
2022-08-28 14:15:20 +01:00
7d18a21734
Editing
2022-08-27 20:49:55 +01:00
d56e217a40
Work on docs. Document config options, expand the intro, move instruction timings and pseudocode to appendices.
2022-08-27 20:13:21 +01:00
a79c857d82
Bump riscv-tests: enable hardware instruction breakpoints in hardware tests
2022-08-27 17:05:02 +01:00
9a60f06c43
Fix trigger enable condition
2022-08-23 01:05:46 +01:00
fef6d80fd4
tcontrol.mpte is not supposed to change on trap exit, unlike mstatus.mpie
2022-08-23 00:19:56 +01:00
9e11c0e5a8
Fix tdata1.dmode being writable from M-mode
2022-08-23 00:08:17 +01:00
04f138ae0e
Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant
2022-08-23 00:05:30 +01:00
Luke Wren