Luke Wren
|
5cc483898d
|
Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
|
2021-07-10 21:02:18 +01:00 |
|
Luke Wren
|
58a6b8b4c8
|
Add 32IM testlist
|
2021-06-05 12:03:05 +01:00 |
|
Luke Wren
|
be79a611e1
|
Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why.
|
2021-06-04 09:19:18 +01:00 |
|
Luke Wren
|
c03bc2efb5
|
Update init.S for new IRQ functionality
|
2021-06-04 08:16:54 +01:00 |
|
Luke Wren
|
12851d3742
|
Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
|
2021-05-30 19:52:46 +01:00 |
|
Luke Wren
|
12205f12c7
|
Add instruction fetch match check
|
2021-05-30 11:22:36 +01:00 |
|
Luke Wren
|
16dc905dce
|
Add simple formal bus properties check
|
2021-05-30 10:19:42 +01:00 |
|
Luke Wren
|
2330b84b73
|
Use .f for riscv-formal tb dependencies, small reshuffling of directories
|
2021-05-30 09:44:57 +01:00 |
|
Luke Wren
|
089bcc7c43
|
Typo
|
2021-05-29 23:24:18 +01:00 |
|
Luke Wren
|
1b252d4bda
|
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
|
2021-05-23 11:59:46 +01:00 |
|
Luke Wren
|
90acfdcbe8
|
Organise test directory into formal and sim
|
2021-05-23 07:42:35 +01:00 |
|
Luke Wren
|
08e986912c
|
Also fix RAW stall on JALR instructions, oops. Runs CoreMark and Dhrystone now
|
2021-05-22 11:18:56 +01:00 |
|
Luke Wren
|
cc6f590f2e
|
Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still
|
2021-05-22 10:16:02 +01:00 |
|
Luke Wren
|
692abbad8b
|
Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
|
2021-05-22 07:55:13 +01:00 |
|
Luke Wren
|
844fa8f97f
|
Rename hazard5 -> hazard3
|
2021-05-21 03:46:29 +01:00 |
|
Luke Wren
|
6dad4e20bb
|
Import from hazard5 9743a1b
|
2021-05-21 02:34:16 +01:00 |