Luke Wren
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763a5cd364
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Add test for readability of all implemented CSRs
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2021-12-11 17:50:12 +00:00 |
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Luke Wren
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c90727b05a
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Remove padding after vector table in init.S
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2021-12-11 12:22:23 +00:00 |
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Luke Wren
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abe1769929
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Add instruction access fault testcase
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2021-12-11 09:54:00 +00:00 |
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Luke Wren
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6d55cd2d55
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Consolidate openocd and bin-load testbenches
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2021-12-11 09:46:38 +00:00 |
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Luke Wren
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3d2c912b4f
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Add test script to make it easier to add software testcases
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2021-12-09 22:25:18 +00:00 |
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Luke Wren
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ac9285846f
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Timer struct in IO header
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2021-12-06 17:16:21 +00:00 |
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Luke Wren
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c5d6be24f3
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Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
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2021-12-04 14:06:48 +00:00 |
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Luke Wren
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ba248c832a
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init.S: also print out mcause when trapping an unhandled exception
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2021-11-29 18:49:37 +00:00 |
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Luke Wren
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1bb7e33b69
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Fix alignment of heap_ptr in init.S. Small ALU cleanup
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2021-11-26 02:59:50 +00:00 |
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Luke Wren
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b0d11c0ab7
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Add RISC-V debug tests
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2021-07-22 17:50:04 +01:00 |
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Luke Wren
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be79a611e1
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Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why.
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2021-06-04 09:19:18 +01:00 |
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Luke Wren
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c03bc2efb5
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Update init.S for new IRQ functionality
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2021-06-04 08:16:54 +01:00 |
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Luke Wren
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12851d3742
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Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
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2021-05-30 19:52:46 +01:00 |
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Luke Wren
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90acfdcbe8
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Organise test directory into formal and sim
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2021-05-23 07:42:35 +01:00 |