Luke Wren
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d1b5f83b7a
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Beef up the ULX3S SoC again now that atomics aren't so disastrous for timing
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2021-12-18 02:41:50 +00:00 |
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Luke Wren
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28b53ef7b5
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Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
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2021-12-18 00:35:13 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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1fa773c67a
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Minimal RV32IMA + debug that fits on iCEBreaker. Not sure why area has regressed so much recently.
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2021-12-05 02:16:54 +00:00 |
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Luke Wren
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8398d7ecb6
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Hook up Zb* extension params on iCEBreaker FPGA
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2021-11-26 01:44:57 +00:00 |
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Luke Wren
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60f364e561
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Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker
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2021-11-21 15:55:52 +00:00 |
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Luke Wren
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9173bcf585
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Experimentally add SPI XIP to SoC (breaks FTDI UART on iCEBreaker -- need to move UART to a PMOD to avoid IO conflict)
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2021-08-21 17:04:15 +01:00 |
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Luke Wren
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924967ee72
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Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k
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2021-07-25 13:41:04 +01:00 |
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Luke Wren
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5976a8a9b7
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Add activity LED to iCEBreaker
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2021-07-25 13:13:41 +01:00 |
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Luke Wren
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6fcc74a043
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Add some instructions to Readme
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2021-07-24 11:53:08 +01:00 |
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Luke Wren
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115cb2c50f
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Tweaks to example soc configuration
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2021-07-23 23:08:23 +01:00 |
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Luke Wren
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2ae30183aa
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Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
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2021-07-23 18:32:47 +01:00 |
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Luke Wren
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14ba030271
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Example soc tweaks, add openocd config
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2021-07-16 20:44:25 +01:00 |
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Luke Wren
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f4952ab66d
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Add simple example SoC, hangs nextpnr for some reason!
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2021-07-13 03:40:06 +01:00 |