Luke Wren
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1fa773c67a
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Minimal RV32IMA + debug that fits on iCEBreaker. Not sure why area has regressed so much recently.
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2021-12-05 02:16:54 +00:00 |
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Luke Wren
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5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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be6b2f3f76
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Fix up DTMs to use byte addressing
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2021-12-02 02:05:23 +00:00 |
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Luke Wren
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1ebccb7cce
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Switch DM to use byte addresses on APB, not word addresses
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2021-12-02 01:47:30 +00:00 |
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Luke Wren
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94a3d43f27
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Add Hazard3's registered marchid value to hdl and docs
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2021-11-28 19:53:49 +00:00 |
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Luke Wren
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8398d7ecb6
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Hook up Zb* extension params on iCEBreaker FPGA
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2021-11-26 01:44:57 +00:00 |
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Luke Wren
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60f364e561
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Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker
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2021-11-21 15:55:52 +00:00 |
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Luke Wren
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9173bcf585
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Experimentally add SPI XIP to SoC (breaks FTDI UART on iCEBreaker -- need to move UART to a PMOD to avoid IO conflict)
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2021-08-21 17:04:15 +01:00 |
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Luke Wren
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70a44d9681
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Small code cleanup
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2021-07-24 10:08:27 +01:00 |
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Luke Wren
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115cb2c50f
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Tweaks to example soc configuration
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2021-07-23 23:08:23 +01:00 |
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Luke Wren
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2ae30183aa
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Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
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2021-07-23 18:32:47 +01:00 |
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Luke Wren
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41477ce479
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Extract DTM bus/control logic from the JTAG-related parts
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2021-07-22 19:26:25 +01:00 |
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Luke Wren
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14ba030271
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Example soc tweaks, add openocd config
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2021-07-16 20:44:25 +01:00 |
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Luke Wren
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f4952ab66d
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Add simple example SoC, hangs nextpnr for some reason!
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2021-07-13 03:40:06 +01:00 |