Luke Wren
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a536e3baa7
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rvcpp sim: add A extension and M-mode traps
(now passes a lot of the Hazard3 tests)
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2023-04-01 08:21:43 +01:00 |
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Luke Wren
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142b3a81ff
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Add spike-extracted output to zcmp_push
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2023-03-20 15:37:38 +00:00 |
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Luke Wren
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7702c44288
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Handle timeout in runtests
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2023-03-20 01:32:16 +00:00 |
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Luke Wren
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399dcf2cb9
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Add test for U-mode X permissions
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2022-05-25 13:47:16 +01:00 |
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Luke Wren
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456810b09e
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Make vcd generation optional in runtests
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2022-05-24 22:56:13 +01:00 |
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Luke Wren
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7cfc976ef2
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Set U RWX permission on all of memory in the U CSR readability test
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2022-05-24 19:58:12 +01:00 |
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Luke Wren
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07d4b23a9a
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Add option to pass test list to runtests
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2022-05-24 16:17:54 +01:00 |
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Luke Wren
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719c21fec3
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Add IRQ tests. Disable waves by default in runtests
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2021-12-12 15:53:04 +00:00 |
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Luke Wren
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a232833d81
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Add CSR writable test
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2021-12-12 14:23:34 +00:00 |
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Luke Wren
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7b1da32af1
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Move expected_output into tests inline
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2021-12-11 16:58:25 +00:00 |
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Luke Wren
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6d55cd2d55
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Consolidate openocd and bin-load testbenches
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2021-12-11 09:46:38 +00:00 |
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Luke Wren
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3d2c912b4f
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Add test script to make it easier to add software testcases
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2021-12-09 22:25:18 +00:00 |