Luke Wren
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185194973f
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Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
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2022-08-06 23:02:08 +01:00 |
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Luke Wren
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9787c604ad
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Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
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2022-07-30 17:31:53 +01:00 |
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Luke Wren
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ee7d8e1947
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Bump embench for script fixes/improvements
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2022-07-07 18:29:37 +01:00 |
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Luke Wren
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91be98f2da
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Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
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2022-07-06 23:53:11 +01:00 |
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Luke Wren
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5a39d8b7e7
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Track minstret and mcycle separately now that the model is cycle-accurate
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2022-07-06 13:50:13 +01:00 |
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Luke Wren
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5dfe5cb62b
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Update rvpy to match current fastest config: stage 2 mul, single BTB entry on backward branches
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2022-07-06 13:49:51 +01:00 |
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Luke Wren
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b7d9defcf2
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Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
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2022-07-05 03:37:19 +01:00 |
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Luke Wren
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27793b25a1
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Rebase riscv-tests against upstream, and pick up new semihosting file io test
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2022-07-04 00:45:20 +01:00 |
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Luke Wren
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e44d2e6f9e
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Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed
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2022-07-03 23:34:12 +01:00 |
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Luke Wren
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b1225c386c
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Add missing 1port SBA change, and update example soc and bus compliance tb to reflect
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2022-07-03 17:57:03 +01:00 |
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Luke Wren
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9e15cd3485
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Add standalone SBA-to-AHB shim, and make SBA off by default in the DM
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2022-07-03 15:30:33 +01:00 |
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Luke Wren
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d5cd3e0681
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Add SBA patch-through to 1-core wrapper.
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
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2022-07-03 15:17:44 +01:00 |
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Luke Wren
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51bc26f8ac
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First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
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2022-07-03 00:25:47 +01:00 |
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Luke Wren
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a7cb214501
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Reduce ROM size in instruction_fetch_match: depth is more useful
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2022-06-26 19:59:44 +01:00 |
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Luke Wren
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5193dfe477
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Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,
and enable it only on the bus compliance model checks. Trying to make
the solver's life easier in instruction_fetch_match.
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2022-06-25 20:08:40 +01:00 |
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Luke Wren
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8ef9d77be8
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Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations.
Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)
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2022-06-25 13:11:40 +01:00 |
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Luke Wren
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d9389fb23e
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Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
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2022-06-16 01:42:28 +01:00 |
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Luke Wren
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f8aad6d2f3
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Fix some bugs, too tired to list them, look at the diff
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2022-06-15 04:05:31 +01:00 |
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Luke Wren
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0766ec6f8a
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First pass at adding branch prediction
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2022-06-15 02:05:46 +01:00 |
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Luke Wren
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3703b1fc4c
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Allow use of cir_flush_behind in frontend_match formal tb
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2022-06-13 20:36:15 +01:00 |
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Luke Wren
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e68d8a6cd6
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Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
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2022-06-13 01:23:32 +01:00 |
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Luke Wren
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23b4dbe7f3
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Redesign fetch queue: 2x32 + 3x16 -> 6x16.
Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
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2022-06-12 02:44:08 +01:00 |
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Luke Wren
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d5a202e4a5
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Add standalone frontend formal tb
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2022-06-11 20:14:24 +01:00 |
|
Luke Wren
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d31b1708db
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Make rvpy cycle-accurate enough to get the correct Dhrystone score
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2022-06-09 01:34:37 +01:00 |
|
Luke Wren
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02b303b385
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Remove stray old expected output file from sw_testcases dir
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2022-06-03 17:20:49 +01:00 |
|
Luke Wren
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e2c9901701
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Update readme for runtests
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2022-05-30 01:12:16 +01:00 |
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Luke Wren
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2cfe6aa90e
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Add test to check MPRV/MPP behaviour when executing an MRET
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2022-05-29 19:51:19 +01:00 |
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Luke Wren
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f96a0ffb75
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Add test for MPRV vs PMP
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2022-05-29 19:06:04 +01:00 |
|
Luke Wren
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71eff7649d
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Add PMP U-mode read/write permission test
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2022-05-29 18:42:44 +01:00 |
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Luke Wren
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c8afcdbb8f
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Extend umode_wfi test to check U-mode WFI doesn't stall the processor if TW=0 or PMP X check fails
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2022-05-29 17:42:15 +01:00 |
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Luke Wren
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460fa0bb4a
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Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.
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2022-05-28 17:22:28 +01:00 |
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Luke Wren
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66965ac073
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Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
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2022-05-28 15:36:21 +01:00 |
|
Luke Wren
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4090f4eb24
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Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat
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2022-05-28 15:01:27 +01:00 |
|
Luke Wren
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9e2f5df00a
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Add testbench flag to propagate CPU return code to testbench return
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2022-05-28 15:00:28 +01:00 |
|
Luke Wren
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81aec325bb
|
ecall from U-mode has a different mcause value than ecall from M-mode
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2022-05-28 12:07:29 +01:00 |
|
Luke Wren
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632c61daba
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Rebase debug tests, pick up two new tests (both pass)
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2022-05-28 11:34:41 +01:00 |
|
Luke Wren
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f2876eb51f
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Fix bad mepc reported after branching to a branch in a no-X address range
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2022-05-27 22:47:04 +01:00 |
|
Luke Wren
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cd3125b6e5
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Add new bus signals on instruction_fetch_match/tb.v
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2022-05-27 21:48:45 +01:00 |
|
Luke Wren
|
b655148148
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Bump riscv-tests for better PMP disable fix
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2022-05-27 21:36:54 +01:00 |
|
Luke Wren
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e208652ad7
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Fix misa value in csr_id test
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2022-05-26 00:48:12 +01:00 |
|
Luke Wren
|
d7787942e9
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Add two new tests to debug test list. Remainder are still non-applicable
|
2022-05-26 00:47:08 +01:00 |
|
Luke Wren
|
a17b941e38
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Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)
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2022-05-25 23:46:23 +01:00 |
|
Luke Wren
|
37f7588bad
|
Fix hazard3 reset vector check value in debug tests
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2022-05-25 21:45:36 +01:00 |
|
Luke Wren
|
5be8835365
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Add missing output to pmp_write_and_lock test
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2022-05-25 15:34:28 +01:00 |
|
Luke Wren
|
399dcf2cb9
|
Add test for U-mode X permissions
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2022-05-25 13:47:16 +01:00 |
|
Luke Wren
|
7340765699
|
Add simple test to read, write and lock PMP registers
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2022-05-25 02:05:24 +01:00 |
|
Luke Wren
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456810b09e
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Make vcd generation optional in runtests
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2022-05-24 22:56:13 +01:00 |
|
Luke Wren
|
64d9f4a111
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Add tests for execution of mret and wfi in U mode
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2022-05-24 22:14:20 +01:00 |
|
Luke Wren
|
20f06c4a02
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Build tb with 4 PMP regions by default
|
2022-05-24 20:06:57 +01:00 |
|
Luke Wren
|
7cfc976ef2
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Set U RWX permission on all of memory in the U CSR readability test
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2022-05-24 19:58:12 +01:00 |