Luke Wren
fbacbe82a7
PPA: simplify generation of uop_atomic and uop_seq_end flags in instr_decompress to be independent of most instruction bits. Add some new assertions on behaviour of uop signals outside of uop sequences.
2024-05-26 16:24:07 +01:00
Luke Wren
2f6e98335f
Add two new tests for IRQs-over-Zcmp, and fix a bug they found:
...
Interrupting the PC-setting step of a cm.popret (only) can sample the return target
as the exception return PC, which will cause the stack pointer adjust to be skipped
when returning from the IRQ. Fix this by making the PC-setting step uninterruptible
(note the PC-setting step is the instruction we execute first out of the group
of instructions specified in the Zc spec as being atomic wrt interrupts. This
does not itself imply that the PC-setting step is uninterruptible, it just
requires that when the PC-setting step retires, all following steps also retire.
However this is not sufficient given the special case logic that allows the jr
ra PC-setting step to execute before the final stack adjust as an optimisation.)
2023-11-03 21:12:21 +00:00
Luke Wren
afcb6d283c
Missing default assignment
2023-03-23 10:57:50 +00:00
Luke Wren
4a1d2b5008
Save a cycle on popret/popretz by executing the stack adjust after the jump
2023-03-23 02:50:34 +00:00
Luke Wren
7607dacfc4
Fix incorrect register order within stack frame for push/pop
2023-03-20 06:32:20 +00:00
Luke Wren
8b73b1b927
Fix mvsa01 r2s decode, Dhrystone runs with Zcb now
2023-03-20 05:03:39 +00:00
Luke Wren
c4e0c15160
Fix hookup of uop_atomic signal
2023-03-20 02:40:49 +00:00
Luke Wren
3b2ddee06b
Fix push/pop frame format, fix source regnums for mvsa01/mva01s
2023-03-20 02:35:18 +00:00
Luke Wren
4aed15540d
Fix destination register for final uop of c.popretz
2023-03-20 01:31:49 +00:00
Luke Wren
6b8923a623
Fix bad predecode of a0/a1 in mvsa01/mva01s.
...
Fix bad pop load offset when extra sp adjust is nonzero.
2023-03-20 01:03:49 +00:00
Luke Wren
e966e832d2
First attempt at Zcmp
2023-03-20 00:19:23 +00:00
Luke Wren
99c0660c3e
Fix decompress of c.sb/c.sh
...
Can now run CoreMark, Hazard3 sw testcases etc using core-v compiler
with Zcb enabled.
2023-03-16 20:36:36 +00:00
Luke Wren
78d937e5c8
Yeet Zcb into core
2023-03-16 18:48:15 +00:00
Luke Wren
96e55a5446
Replace localparams with defines in rv_opcodes.vh, to avoid slightly dubious localparam to casez Z-propagation
2022-08-20 16:22:04 +01:00
Luke Wren
d299a3ca4e
More width tweaks
2022-08-20 16:11:58 +01:00
Luke Wren
bc274867c0
More width mismatch fixes
2022-08-20 15:27:14 +01:00
Luke Wren
dbe9a7824a
Cleanup of some width mismatches in instruction decompress
2022-08-20 14:58:41 +01:00
Luke Wren
ea2b8888a4
Update copyright years
2022-06-09 00:12:01 +01:00
Luke Wren
b0d28447ab
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
Luke Wren
e05e9a4109
Add default_nettype none at top of every file, and default_nettype wire at bottom
2021-11-23 22:10:39 +00:00
Luke Wren
af684c4e82
Some cleanup; correctly decode 16-bit EBREAK
2021-06-03 20:03:43 +01:00
Luke Wren
844fa8f97f
Rename hazard5 -> hazard3
2021-05-21 03:46:29 +01:00