d9389fb23e
Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
2022-06-16 01:42:28 +01:00
f8aad6d2f3
Fix some bugs, too tired to list them, look at the diff
2022-06-15 04:05:31 +01:00
0766ec6f8a
First pass at adding branch prediction
2022-06-15 02:05:46 +01:00
3703b1fc4c
Allow use of cir_flush_behind in frontend_match formal tb
2022-06-13 20:36:15 +01:00
e68d8a6cd6
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
2022-06-13 01:23:32 +01:00
26d54d0023
Re-rewrite frontend to track the halfword-validity of in-flight transfers, and clean up the old cir_lock mechanism to be a modified flush
2022-06-12 21:01:39 +01:00
e3da922f8b
Revert previous frontend changes. Seemed promising but is a dead end for area.
...
The original frontend design can probably be tweaked to support predictions.
2022-06-12 16:25:42 +01:00
940b7e4009
Actually still need 7 halfwords for full throughput in the case of sequential word-sized halfword-aligned instructions
2022-06-12 16:21:56 +01:00
8458dff083
Fix bus errors not being applied in frontend
2022-06-12 05:28:21 +01:00
23b4dbe7f3
Redesign fetch queue: 2x32 + 3x16 -> 6x16.
...
Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
2022-06-12 02:44:08 +01:00
d5a202e4a5
Add standalone frontend formal tb
2022-06-11 20:14:24 +01:00
3b5879da66
Small code cleanup in frontend. The address phase alignment state no longer needs to be tracked, since we just generate word accesses always, for simplicity.
2022-06-11 14:27:59 +01:00
de9b51b787
Remove default zeroing of fetch address when no fetch is asserted -- this puts LUTs on a critical path and arguably causes more toggling than asserting the sequentially next address by default.
2022-06-11 14:26:40 +01:00
d31b1708db
Make rvpy cycle-accurate enough to get the correct Dhrystone score
2022-06-09 01:34:37 +01:00
11596a5bd7
Remove unused/untested RISC-V timer implementation
2022-06-09 00:12:26 +01:00
ea2b8888a4
Update copyright years
2022-06-09 00:12:01 +01:00
02b303b385
Remove stray old expected output file from sw_testcases dir
2022-06-03 17:20:49 +01:00
ae2784d0ea
PMP config: separate granularity config from hardwired region config. Give correct read value for G > 1.
2022-06-03 17:09:43 +01:00
e0a9fb7312
Add option to hardwire PMP regions, or reduce their granularity
2022-06-03 01:19:03 +01:00
b823132a6e
Remove experimental description from U-mode and PMP. Add list of specifications.
2022-05-31 01:24:36 +01:00
e2c9901701
Update readme for runtests
2022-05-30 01:12:16 +01:00
2cfe6aa90e
Add test to check MPRV/MPP behaviour when executing an MRET
2022-05-29 19:51:19 +01:00
f96a0ffb75
Add test for MPRV vs PMP
2022-05-29 19:06:04 +01:00
71eff7649d
Add PMP U-mode read/write permission test
2022-05-29 18:42:44 +01:00
c8afcdbb8f
Extend umode_wfi test to check U-mode WFI doesn't stall the processor if TW=0 or PMP X check fails
2022-05-29 17:42:15 +01:00
460fa0bb4a
Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.
2022-05-28 17:22:28 +01:00
66965ac073
Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
2022-05-28 15:36:21 +01:00
4090f4eb24
Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat
2022-05-28 15:01:27 +01:00
9e2f5df00a
Add testbench flag to propagate CPU return code to testbench return
2022-05-28 15:00:28 +01:00
81aec325bb
ecall from U-mode has a different mcause value than ecall from M-mode
2022-05-28 12:07:29 +01:00
632c61daba
Rebase debug tests, pick up two new tests (both pass)
2022-05-28 11:34:41 +01:00
f2876eb51f
Fix bad mepc reported after branching to a branch in a no-X address range
2022-05-27 22:47:04 +01:00
cd3125b6e5
Add new bus signals on instruction_fetch_match/tb.v
2022-05-27 21:48:45 +01:00
b655148148
Bump riscv-tests for better PMP disable fix
2022-05-27 21:36:54 +01:00
0e462574b2
Move declaration of x_exec_pmp_fail to before its first use
2022-05-27 15:04:43 +01:00
e208652ad7
Fix misa value in csr_id test
2022-05-26 00:48:12 +01:00
d7787942e9
Add two new tests to debug test list. Remainder are still non-applicable
2022-05-26 00:47:08 +01:00
156fbcd019
Update behaviour of mstatus.mpp and mprv on mret to match priv-1.12 spec
2022-05-26 00:42:50 +01:00
a17b941e38
Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)
2022-05-25 23:46:23 +01:00
37f7588bad
Fix hazard3 reset vector check value in debug tests
2022-05-25 21:45:36 +01:00
0efcf53fe5
Fix X PMP fail not suppressing load/store address phase.
...
Fix PMP-failed load/store still passing on a data phase tag to stage 3.
Fix WFI still pausing the core after a PMP X fail.
2022-05-25 16:18:03 +01:00
5be8835365
Add missing output to pmp_write_and_lock test
2022-05-25 15:34:28 +01:00
399dcf2cb9
Add test for U-mode X permissions
2022-05-25 13:47:16 +01:00
e2b9a3b2f9
Fix two PMP-related bugs:
...
1. Generating PMP load/store exceptions when the instruction is not a load/store
2. Passing a PMP exec permission exception into M whilst the frontend is still
starved, causing early taking of the exception and a bad mepc value.
2022-05-25 13:23:44 +01:00
7340765699
Add simple test to read, write and lock PMP registers
2022-05-25 02:05:24 +01:00
456810b09e
Make vcd generation optional in runtests
2022-05-24 22:56:13 +01:00
64d9f4a111
Add tests for execution of mret and wfi in U mode
2022-05-24 22:14:20 +01:00
51750eb81d
Add mstatus.tw to control U-mode WFI, and prevent mret execution in U-mode.
2022-05-24 21:12:44 +01:00
10ca3aec80
Add U-mode and PMP to readme
2022-05-24 20:41:25 +01:00
20f06c4a02
Build tb with 4 PMP regions by default
2022-05-24 20:06:57 +01:00
Luke Wren
Luke Wren