Luke Wren
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ebe87dce46
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Reorganise CSR section of docs
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2021-12-02 01:35:18 +00:00 |
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Luke Wren
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c5e85dea4c
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Add mconfigptr CSR
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2021-12-01 03:25:56 +00:00 |
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Luke Wren
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94a3d43f27
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Add Hazard3's registered marchid value to hdl and docs
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2021-11-28 19:53:49 +00:00 |
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Luke Wren
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0fafae1ab1
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Regenerate PDF
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2021-11-28 16:27:54 +00:00 |
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Luke Wren
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e7466ae4be
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Move DM data0 CSR into the M-custom space, and document this
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2021-11-28 15:52:52 +00:00 |
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Luke Wren
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9bf4d5105f
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Describe possible debug topologies. Update pdf.
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2021-11-28 09:01:23 +00:00 |
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Luke Wren
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4e2686d4ab
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Finish documenting CSRs. Draw a debug topology diagram.
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2021-11-28 08:17:23 +00:00 |
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Luke Wren
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76172cdade
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Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
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2021-11-28 06:33:35 +00:00 |
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Luke Wren
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79c29354d2
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Update docs with bitmanip instructions
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2021-11-28 03:16:45 +00:00 |
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Luke Wren
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2aac3d4f91
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Add attempt at CPU backend diagram
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2021-11-23 22:14:55 +00:00 |
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Luke Wren
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b0d11c0ab7
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Add RISC-V debug tests
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2021-07-22 17:50:04 +01:00 |
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Luke Wren
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e4b0d999cb
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Minor doc updates
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2021-07-18 20:45:08 +01:00 |
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Luke Wren
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46f95f859d
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Some doc updates
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2021-07-17 13:07:09 +01:00 |
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Luke Wren
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93c7039ea1
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Sync doc updates
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2021-07-12 22:13:31 +01:00 |
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Luke Wren
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47fa7f4d10
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Associated doc updates
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2021-07-10 18:53:59 +01:00 |
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Luke Wren
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83244c6651
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Add Read ID command to UART DTM
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2021-07-10 16:14:35 +01:00 |
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Luke Wren
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3312ea7022
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Add draft UART DTM
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2021-07-08 17:57:46 +01:00 |
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Luke Wren
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5f8d217395
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Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
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2021-05-31 17:54:12 +01:00 |
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Luke Wren
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4053458485
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Document some IRQ CSRs, and instruction timings
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2021-05-31 15:57:05 +01:00 |