Luke Wren
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ae11d04b10
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Add HMASTER output to processor wrappers, to indicate when the bus cycle is driven by SBA rather than the core
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2022-07-03 18:02:47 +01:00 |
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Luke Wren
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b1225c386c
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Add missing 1port SBA change, and update example soc and bus compliance tb to reflect
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2022-07-03 17:57:03 +01:00 |
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Luke Wren
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ea2b8888a4
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Update copyright years
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2022-06-09 00:12:01 +01:00 |
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Luke Wren
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2df1179994
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Wire privilege through from core to bus masters. Tied off inside core.
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2022-05-24 14:05:26 +01:00 |
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Luke Wren
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0a369efc06
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Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
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2021-12-18 15:41:05 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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e05e9a4109
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Add default_nettype none at top of every file, and default_nettype wire at bottom
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2021-11-23 22:10:39 +00:00 |
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Luke Wren
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d03a82a826
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Add instruction fetch faults
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2021-09-04 02:57:39 +01:00 |
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Luke Wren
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d9300ee127
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Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry
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2021-07-17 19:26:45 +01:00 |
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Luke Wren
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5aca6be572
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Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.
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2021-07-16 18:28:30 +01:00 |
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Luke Wren
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f4952ab66d
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Add simple example SoC, hangs nextpnr for some reason!
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2021-07-13 03:40:06 +01:00 |
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Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
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Luke Wren
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5f8d217395
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Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
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2021-05-31 17:54:12 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |