Luke Wren 5db6c68c56 Update riscv-tests for correct misa.x value		2021-12-04 11:19:43 +00:00
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bitmanip-random	Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation	2021-11-27 17:19:41 +00:00
common	init.S: also print out mcause when trapping an unhandled exception	2021-11-29 18:49:37 +00:00
coremark	Move DM data0 CSR into the M-custom space, and document this	2021-11-28 15:52:52 +00:00
dhrystone	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
ecall_simple	Update init.S for new IRQ functionality	2021-06-04 08:16:54 +01:00
embench	Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.	2021-12-04 01:17:57 +00:00
hellow	Add some instructions to Readme	2021-07-24 11:53:08 +01:00
openocd	Fix up DTMs to use byte addressing	2021-12-02 02:05:23 +00:00
riscv-compliance	Add 32IM testlist	2021-06-05 12:03:05 +01:00
riscv-tests	Update riscv-tests for correct misa.x value	2021-12-04 11:19:43 +00:00
rvcpp	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
rvpy	Correct mnemonic when logging unsigned sltiu instruction	2021-10-08 12:02:37 +01:00
tb_cxxrtl	Add option for fast high-half multiplies	2021-11-29 18:48:02 +00:00
wfi_loop	Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench	2021-11-06 09:59:27 +00:00