Luke Wren c57a80f358 Add AMO + timer testcase		2021-12-06 07:47:20 +00:00
..
amo_smoke	First plausibly working AMOs. Add AMOs to instruction timings list	2021-12-04 23:44:22 +00:00
amo_timer_irq	Add AMO + timer testcase	2021-12-06 07:47:20 +00:00
bitmanip-random	Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation	2021-11-27 17:19:41 +00:00
common	Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.	2021-12-04 14:06:48 +00:00
coremark	Move DM data0 CSR into the M-custom space, and document this	2021-11-28 15:52:52 +00:00
dhrystone	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
ecall_simple	Update init.S for new IRQ functionality	2021-06-04 08:16:54 +01:00
embench	Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.	2021-12-04 01:17:57 +00:00
hellow	Add some instructions to Readme	2021-07-24 11:53:08 +01:00
lr_sc_smoke	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
openocd	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
riscv-compliance	Bump to latest version of riscv-arch-test	2021-12-06 02:18:48 +00:00
riscv-tests	Update riscv-tests for correct misa.x value	2021-12-04 11:19:43 +00:00
rvcpp	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
rvpy	Correct mnemonic when logging unsigned sltiu instruction	2021-10-08 12:02:37 +01:00
tb_cxxrtl	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
wfi_loop	Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench	2021-11-06 09:59:27 +00:00