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58 Commits

Author SHA1 Message Date
chxin66 ea8046ec9c
Added roi_align layoutinfer & cases (#615) 
* Added roi_align layoutinfer & cases

Type: New feature

Signed-off-by: Chen <jack.chen@verisilicon.com>

* Update instancenorm op spec .json

Type: bug fix

Signed-off-by: Chen <jack.chen@verisilicon.com>

* Added roi_pool layoutinfer & fixed case bug

Type: new feature

Signed-off-by: Chen <jack.chen@verisilicon.com>

---------

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
 2023-07-08 23:39:56 +08:00
Chen Feiyue 75882d4195
Added new_axis_mask param for stridedslice (#600) 
Add another constructor for stridedslice when new_axis_mask is set

The layout inference need to reconstruct the axis mapping when
new_axis_mask is set(TODO)

Type: New Feature

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-06-25 09:24:41 +08:00
Chen Feiyue d823ef6fcb
Remove unused value in op layoutinfer (#607) 
Remove unused value to make sure project build successfully with higher
version compiler such as clang15

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-06-25 09:23:09 +08:00
chxin66 26b4e53fe7
fixed reduce layoutinfer bug (#605) 
Type: Bug fixed

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
 2023-06-19 21:56:08 +08:00
chxin66 ea8adc456a
fixed instance norm bug & add its layoutinfer (#593) 
Type: Bug fix

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
 2023-05-31 12:55:42 +08:00
chxin66 4f92e58155
optimization for tiny_yolov4 (#591) 
Type: code improvment

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
 2023-05-23 14:28:47 +08:00
Chen Feiyue 3c5ee7a46e
Refine prelu layout inference (#577) 
In the past we reverse all inputs to default order pv and caused
unnecessary transpose operation.
In this commit  only const slope  will be handled and do transpose if necessary.

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-04-25 11:25:55 +08:00
chxin66 c2755b90ea
Fixed l2normalization layout infer bug (#570) 
And added a case

Type: Bug fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2023-03-27 15:00:25 +08:00
Zhouheng Zheng e49f67b840
Remove tensor GetDataRef api (#569) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2023-03-23 21:35:30 +08:00
zhouheng.zheng 958b26e499 Fix mirror pad param mismatch 2023-03-21 09:20:00 +08:00
Chen Xin e71d537042 Fixed deconv2d layout infer bug 
Type: Bug fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2023-02-20 13:06:24 +08:00
Chen Xin 5e7f5cecea Fixed grouped_conv2d layout infer & Added cases 
added cases for conv2d/grouped_conv2d

Type: Bug fixed

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2023-01-20 15:28:21 +08:00
Tang d778dfb82d update copyright information 2023-01-20 12:49:48 +08:00
Chen Xin 58d36ab943 Added reduce_all layoutinfer & reduce cases 
Type: New feature
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2023-01-09 09:30:44 +08:00
Chen Xin c1f8a959af Fixed bug for pad_v2 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-30 10:19:03 +08:00
Chen Xin 0e211c8efd Fixed (groupd)conv2d layout infer bug 
And added a weight_as_input case to test

Type: Bug Fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-16 15:20:56 +08:00
Chen Xin 7582b57edc Added pad_v2 & pad_v2 layout infer 
And added 4 rank case

Type: Added new op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-16 15:03:58 +08:00
Feiyue Chen c231c54a66 Fixed BidirectionalSequenceRnn bugs 
Added layout inference for BidirectionalRnn
Fixed wrong datatype and wrong output order of internal about backward rnn
Corrected golden in BidirectionalRnn&BidirectionalRnnExt unit test
Modified  copyright and log message

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-28 09:45:50 +08:00
Feiyue Chen 05a1c561af Added layout_inference for UnidirectionalRnn 
Added layout_inference so that can support tflite cases
Modified copyright of code
Modified case name and value name in UnidirectionalRnn unittest

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-23 20:58:00 +08:00
Chen Xin 9fe7b955e5 Fixed average pool layout infer 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-16 13:34:31 +08:00
Chen Xin 535c9da867 Fixed bug when input's index is not 0 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-28 16:48:16 +08:00
Chen Xin 72f2c5b69e Supported composed layout infer & added unit test 
Fixed fc layout infer in rnncell layout infer
 2022-09-26 14:29:46 +08:00
Chen Xin 9b13b6f677 Replace name direct_map_op with builtin_op 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-19 10:21:19 +08:00
chxin66 cfe8c808bd
Added broadcast layout infernece (#438) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-27 12:52:48 +08:00
chxin66 9f331ed5ec
Added batch dims in gather (#435) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-19 12:33:09 +08:00
chxin66 f52cb852d6
Fixed transpose layout inference bug (#430) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-11 09:55:48 +08:00
chxin66 3e8d5e3493
Added grouped conv2d layout inference (#419) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-06-28 14:52:26 +08:00
chxin66 44cc6f9f09
lstm layout inference & Added unidirectional lstm layout inference (#392) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-29 22:40:43 +08:00
Sven 4f2991c853
Fixed no-output if transpose is last op and can be optimized (#395) 
* Fixed no-output if transpose is last op and can be optimized

If transpose can be erased by layout inference, replace it as a
reshape - input and output have same shape - expect low-level
optimization erase the reshape

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-05-13 16:59:25 +08:00
chxin66 11572140d2
Fixed layout inference bug for stack (#375) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-05 17:18:09 +08:00
chxin66 5c4800ab33
Fixed pad layout inference bug & added one stridedslice case (#370) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-20 21:44:43 +08:00
chxin66 eb21143987
Support specifying pad_mode in pad (#355) 
https://github.com/VeriSilicon/TIM-VX/issues/307

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:55:47 +08:00
chxin66 93f20429ea
Fixed layout inference bug for stride_slice (#329) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 10:12:37 +08:00
chxin66 1ca89d2ffa
Add layout inference & layout test for stack (#337) 
* Added layout inference & layout test for stack

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-06 13:01:41 +08:00
liyuenan fe31a47bf9
enable no bias in FC layout inference (#294) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-02-21 19:09:38 +08:00
Antkillerfarm 36e6afa567
add alpha & beta parameters for HardSigmoid (#265) 2022-01-13 14:17:19 +08:00
Zongwu.Yang 4229ad88b3
support conv3d (#238) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2022-01-11 14:13:15 +08:00
liyuenan 6275f84575
Fix the conflict for previous two commits (#253) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-29 15:38:42 +08:00
chxin66 cea11422b8
Added RNNCell & unit test (#249) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-29 11:08:24 +08:00
liyuenan 75d39e2cfd
Support layout inference for transpose (#250) 
Added interface GetProdeucerOp(tensor) in Graph


Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-29 11:06:28 +08:00
Zongwu.Yang aed3a48248
Add layout inference and unit test for BatchNorm (#243) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-12-22 09:47:57 +08:00
Sven e42faad710
Fix build issue if 40BIT_VA enabled (#240) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-12-17 15:00:14 +08:00
liyuenan 2c38f89d06
Catch the correct output when output has consumer (#239) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-15 09:54:54 +08:00
Antkillerfarm b38bd41933
add DataLayout::IcOcWH for TVM usage (#231) 2021-11-30 21:33:14 +08:00
Zhouheng Zheng 68b5acbe7c
Fix layout inference bug for resize layer(#205) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2021-11-04 19:13:21 +08:00
Goose Bomb 914e280209
Refactor CMake build system (#184) 
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test
 2021-10-12 10:44:49 +08:00
xiang.zhang 994f8a9c2a Fixed layout inference crash(assert) if node have multiply output 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-09-16 10:55:29 +08:00
yuenan.li 29f1efc492 add API 'Clone' to tim_vx op and support default layout inference 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 12:29:18 +08:00
yuenan.li 98b9759663 Refine arg in layout inference 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-29 11:24:28 +08:00
yuenan.li 1e42cfd668 Support layout inference for nbg 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-24 17:28:02 +08:00