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348 Commits

Author SHA1 Message Date
meseraph cc34b5f0ea mapped pool1d 2022-12-30 10:52:28 +08:00
Chen Xin aa0b474c19 Added a case for fc 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-30 10:34:21 +08:00
Chen Xin c1f8a959af Fixed bug for pad_v2 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-30 10:19:03 +08:00
Chen Xin 0e211c8efd Fixed (groupd)conv2d layout infer bug 
And added a weight_as_input case to test

Type: Bug Fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-16 15:20:56 +08:00
Feiyue Chen ac4517b5c1 Added EmbeddingLookup 4d support internal 
Added EmbeddingLookup internal support for 4d lut input

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-16 15:09:19 +08:00
Feiyue Chen 06b88e7940 Fixed nn_params in groupconv2d 
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-16 15:08:14 +08:00
Feiyue Chen c6919248e1 fixed groupconv2d params in internal 
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-16 15:04:54 +08:00
Chen Xin 7582b57edc Added pad_v2 & pad_v2 layout infer 
And added 4 rank case

Type: Added new op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-16 15:03:58 +08:00
Feiyue Chen 8d8f4b6e68 Added EmbeddingLookup & deprecate LshProjection 
Added EmbeddingLookup and unit test
Changed LshProjection op status to Deprecated

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-05 09:59:56 +08:00
Qin.Chen 13da73bbe3 Fix maxpoolgrad, hide unused pool value output 
Type: Bug Fix
 2022-12-01 15:49:38 +08:00
Feiyue Chen b7478f7872 Added invalidate handle marco 
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-01 15:37:33 +08:00
Feiyue Chen f7b49ae4e2 Modified README.md about rnn&lstm 
Changed status of UnidirecitonalRnn&BidirectionalRnn
Changed status and internal op of BidirectionalLstm

Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-01 10:56:48 +08:00
Feiyue Chen dd7cd2504c Added HashtableLookup Op 
Added HashtableLookup Op and unit test

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-01 10:55:21 +08:00
Feiyue Chen c231c54a66 Fixed BidirectionalSequenceRnn bugs 
Added layout inference for BidirectionalRnn
Fixed wrong datatype and wrong output order of internal about backward rnn
Corrected golden in BidirectionalRnn&BidirectionalRnnExt unit test
Modified  copyright and log message

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-28 09:45:50 +08:00
Feiyue Chen 05a1c561af Added layout_inference for UnidirectionalRnn 
Added layout_inference so that can support tflite cases
Modified copyright of code
Modified case name and value name in UnidirectionalRnn unittest

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-23 20:58:00 +08:00
Qin.Chen 8cd5bd93ce Add BUILD_WITH_BAZEL option, marco of VSI_FEAT_OP_XXX should behind headers now. 2022-11-22 21:39:02 +08:00
Tang d723ffaf51 fix typo for graph_test.cc 2022-11-22 21:37:40 +08:00
Chen Xin 545d677160 diabled a failed case 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-22 21:36:41 +08:00
Chen Xin 9fe7b955e5 Fixed average pool layout infer 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-16 13:34:31 +08:00
meseraph 883334e1bb add rnn 2022-11-16 13:33:39 +08:00
Feiyue Chen 11fd278d7a Fixed BidirectionalSequenceLSTM bug 
Fixed input error of  the backward direction
Fixed golden error of unit test

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-16 13:31:23 +08:00
Kee 4db479ece4 Set RNN internal dtype 
Init RNN internal dtype to avoid the
internal FC OP to go to the CPU path

Type:Code Improvement

Signed-off-by: Kee <xuke537@hotmail.com>
 2022-11-14 09:39:27 +08:00
Chen Xin 6816a0188a Added minimum unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-11 18:03:46 +08:00
Chen Xin 8867c8de35 Fixed roi_align golden mismatch error 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-11 18:02:36 +08:00
Feiyue Chen ed162d0176 Update internal for 22Q3 release 
update internal to commit-id: e2b0fde631fce349e0e3ad42b2a4d40ce7634a97

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-24 15:34:53 +08:00
Chen Xin 3fed6d6757 fixed bug when broadcast dimensions is negative 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-10-08 21:42:02 +08:00
Feiyue Chen a038df2a84 added transpose_test from https://github.com/VeriSilicon/TIM-VX/issues/429 2022-10-08 14:47:07 +08:00
Chen Xin 20db77ee61 Added two cases in strided_slice 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-29 20:24:09 +08:00
Chen Xin 535c9da867 Fixed bug when input's index is not 0 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-28 16:48:16 +08:00
Chen Xin 4c6299e7fd Added two reduce layout infer unittest 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-28 09:37:38 +08:00
Chen Xin 72f2c5b69e Supported composed layout infer & added unit test 
Fixed fc layout infer in rnncell layout infer
 2022-09-26 14:29:46 +08:00
Feiyue Chen 1802e558ad modified cumsum header && resolve conflict in README.md 2022-09-26 14:27:48 +08:00
Feiyue Chen 264e491d2a added cumsum op & added handle api after BindInput 2022-09-26 14:27:48 +08:00
Feiyue Chen 9cb37b920f added MaxPool3d op 2022-09-26 13:32:56 +08:00
Feiyue Chen 8b8d09aea3 added Rcp op & modified test_utils 2022-09-22 12:15:02 +08:00
Feiyue Chen 1b07b022e2 added sign & softsign 2022-09-20 22:49:45 +08:00
Feiyue Chen f4d5e170de added & modified copyright of some files 2022-09-20 22:47:33 +08:00
Feiyue Chen 84b464ee8b Update README.md 2022-09-20 22:47:33 +08:00
Feiyue Chen 6099022f00 added Mod op & Mod unit test 2022-09-20 22:47:33 +08:00
Chen Xin 9b13b6f677 Replace name direct_map_op with builtin_op 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-19 10:21:19 +08:00
Feiyue Chen 113c3722cb supported int16 dfp quantization & added conv2d unit test 2022-09-15 22:15:22 +08:00
Feiyue Chen 95401036ab fixed some errs on gcc12 2022-09-15 21:26:43 +08:00
Chen Xin 6d9ed7b25b Disabled a conv3d case 
because of some branches are not fully supported

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-15 10:46:05 +08:00
Chen Xin 0bb547b8e4 disabled two Div cases 
int32 type not supported in branch 234062
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-06 23:58:03 +08:00
Chen Xin e62b62015d Added conv3d unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-06 11:45:24 +08:00
xiang.zhang e9771746ba Fix error in feature compatiable guard 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-09-05 15:05:50 +08:00
Chen Xin f348c8e36c disabled two not supported cases 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-05 14:52:59 +08:00
Sven 9de8df404c
Feat: disable maxpoolwithargmax2 feature if no low-level feature avaiable (#471) 
Convert operation list as compiler flags in cmake, when add new
operation in tim-vx, always check if the feature define is available or
not - so that tim-vx can compile with legacy ovxlib library.

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-09-01 18:56:49 +08:00
Chen Xin f6121140b0 Mapped unidirectional gru & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:27:05 +08:00
Chen Xin 58395cf7a7 Modified bidirectional_sequence_lstm golden accuracy 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:26:07 +08:00
root 80fed36ea3 Modified Div_int unit test golden 
Signed-off-by: root <root@DESKTOP-K365DSV.localdomain>
 2022-08-30 10:28:09 +08:00
Chen Xin 1c640c6f10 Mapped bidirectional lstm & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-22 10:42:05 +08:00
Kee 96d186c8d2 Set graph attributes when compile graph to binary 
Keep the same graph attributes as compile graph

Signed-off-by: Kee <xuke537@hotmail.com>
 2022-08-15 06:34:08 +08:00
Chen Xin 944fdfad8f Mapped GRUCell & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 20:34:19 +08:00
Chen Xin 03b5ec2d17 Added div int32 unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 14:37:34 +08:00
Tang a5ba633fe4 add readme for ovxlib_bin_build.sh 2022-08-08 16:52:45 +08:00
yuenan.li 9a28ff5758 Fix the build error for clang when export TIM_VX_ENABLE_PLATFORM=ON 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-08-08 16:50:25 +08:00
Chen Xin 3663a99e0f Fixed param compute bug for lrn 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-04 21:35:59 +08:00
ZhangXiang 6d47ee3ac1 Expose hw feature : isClOnly() 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-08-03 09:06:32 +08:00
Chen Xin 27b4298b29 Fixed quantize param in reduce_sum 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-29 11:12:09 +08:00
qin.chen 9ebddb5452 add op: maxpoolwithargmax2 and maxpoolgrad 2022-07-29 11:11:33 +08:00
qin.chen 84d76e5251 fixed: maxpoolwithargmax's output1 have wrong shape, internal id: I7d5aeab58038bacb73373a4ff4f48a12bb6441db 2022-07-29 11:11:33 +08:00
Antkillerfarm 32241dc4ad
Rename RoiAlign & RoiPool (#446) 2022-07-29 11:10:25 +08:00
chxin66 96c9d5df01
Added cases for reduce sum (#441) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-27 12:53:56 +08:00
chxin66 cfe8c808bd
Added broadcast layout infernece (#438) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-27 12:52:48 +08:00
liyuenan 7d88a668e3
Update internal for 22Q2 release (#432) 
* Update internal for 22Q2 release

update to internal commit-id: e96103281b08404cabb9b65306587627cfa3cb93

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

* Update prebuilt for 22Q2 release

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-07-25 09:29:22 +08:00
chxin66 9f331ed5ec
Added batch dims in gather (#435) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-19 12:33:09 +08:00
chxin66 f52cb852d6
Fixed transpose layout inference bug (#430) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-11 09:55:48 +08:00
chxin66 6344379469
Disabled 3 failed case (#428) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-11 09:54:42 +08:00
liyuenan 24fa582a56
Enable SetRoundingPolicy (#426) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-07-06 17:03:54 +08:00
chxin66 e047fce59f
Disable cases which offloaded to SW path(#422) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-04 15:37:06 +08:00
chxin66 3e8d5e3493
Added grouped conv2d layout inference (#419) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-06-28 14:52:26 +08:00
Antkillerfarm 3dd6c507d4
add reshape unit test (#416) 2022-06-23 14:07:38 +08:00
MESeraph 11f953b506
Mapped roi_pool & added unit test (#404) 
* Mapped roi_pool & added unit test

* modify roialign/roipool unit test
 2022-05-30 19:57:50 +08:00
chxin66 44cc6f9f09
lstm layout inference & Added unidirectional lstm layout inference (#392) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-29 22:40:43 +08:00
MESeraph 6d0c6b01b5
modify GatherElements (#406) 2022-05-29 22:25:14 +08:00
chxin66 1b4c30e572
Mapped roi_align & added unit test (#402) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-27 16:34:48 +08:00
Dahan Gong f8741b4704
feat(tensor): support external buffer when creating input/output tensors (#389) 
* support external buffer when creating input/output tensors

* feat(tensor): add new map/unmap APIs
 2022-05-18 23:38:26 +08:00
Sven a9764291b0
Fix build issue (#397) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-05-16 14:24:44 +08:00
Sven 4f2991c853
Fixed no-output if transpose is last op and can be optimized (#395) 
* Fixed no-output if transpose is last op and can be optimized

If transpose can be erased by layout inference, replace it as a
reshape - input and output have same shape - expect low-level
optimization erase the reshape

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-05-13 16:59:25 +08:00
Antkillerfarm b3677305c4
add GetElementNum/GetElementByteSize/GetByteSize for TensorSpec (#393) 2022-05-13 14:29:25 +08:00
chxin66 0d8ac3dc2b
Added gather_elements & unit test (#363) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-10 09:55:50 +08:00
chxin66 60cfea53a0
fix gather_element operation input num issue (#388) 
Change-Id: Id2e685cf6993776e6674f528b71eb842420b16ad

 Author:    Xia Kaihong <kaihong.xia@verisilicon.com>
 Date:      Thu Apr 14 16:23:16 2022 +0800
 2022-05-06 09:31:14 +08:00
Antkillerfarm c6847981e6
add macro VSI_EXPAND_BROADCAST_ENABLE_DIMENSIONS for unit test compatibility (#386) 2022-05-06 09:30:26 +08:00
chxin66 11572140d2
Fixed layout inference bug for stack (#375) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-05 17:18:09 +08:00
MESeraph eab0d807a6
Added Ceil & unit test (#381) 
* Added Ceil & unit test

* Added Round & Unit test
 2022-05-05 17:11:31 +08:00
chxin66 7a8ae32f73
Added topk & unit test (#384) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-05 17:06:39 +08:00
Zhouheng Zheng c09cdf79ad
fix bug of param num in custom op (#385) 
ref to:https://github.com/VeriSilicon/TIM-VX/issues/378

Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-05-05 17:04:38 +08:00
Antkillerfarm 3f2e67b65f
add macro VSI_EXPAND_BROADCAST_ENABLE_DIMENSIONS for ovxlib compatibility (#374) 2022-04-24 18:38:56 +08:00
Antkillerfarm dbb3631d4e
rename CopyTensorToData to CopyDataFromTensor to align name of tim::vx::Tensor (#373) 2022-04-24 13:36:51 +08:00
chxin66 5c4800ab33
Fixed pad layout inference bug & added one stridedslice case (#370) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-20 21:44:43 +08:00
Sven b5c4514b94
Update operator support planw (#367) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-04-19 11:38:07 +08:00
Antkillerfarm b916e1301a
Add Broadcast op (#365) 2022-04-18 15:45:15 +08:00
chxin66 96dedc1453
Added selu & celu & unit test (#366) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-18 14:35:29 +08:00
Antkillerfarm 954d264108
add BroadcastInDim to internal expand_broadcast op (#364) 2022-04-18 13:59:18 +08:00
chxin66 eb21143987
Support specifying pad_mode in pad (#355) 
https://github.com/VeriSilicon/TIM-VX/issues/307

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:55:47 +08:00
chxin66 479fc576ae
Suported specifying CRD_mode & DCR_mode in depthtospace (#362) 
https://github.com/VeriSilicon/TIM-VX/issues/304

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:53:32 +08:00
chxin66 0dc38eac2e
Added unit test for maxpool (#361) 
https://github.com/VeriSilicon/TIM-VX/issues/318

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 22:16:47 +08:00
lucklee 12746cb4d7
refine tim_internal.cmake for ovxlib vip (#360) 2022-04-13 22:14:32 +08:00
chxin66 93f20429ea
Fixed layout inference bug for stride_slice (#329) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 10:12:37 +08:00