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285 Commits

Author SHA1 Message Date
Feiyue Chen c231c54a66 Fixed BidirectionalSequenceRnn bugs 
Added layout inference for BidirectionalRnn
Fixed wrong datatype and wrong output order of internal about backward rnn
Corrected golden in BidirectionalRnn&BidirectionalRnnExt unit test
Modified  copyright and log message

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-28 09:45:50 +08:00
Feiyue Chen 05a1c561af Added layout_inference for UnidirectionalRnn 
Added layout_inference so that can support tflite cases
Modified copyright of code
Modified case name and value name in UnidirectionalRnn unittest

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-23 20:58:00 +08:00
Qin.Chen 8cd5bd93ce Add BUILD_WITH_BAZEL option, marco of VSI_FEAT_OP_XXX should behind headers now. 2022-11-22 21:39:02 +08:00
Tang d723ffaf51 fix typo for graph_test.cc 2022-11-22 21:37:40 +08:00
Chen Xin 545d677160 diabled a failed case 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-22 21:36:41 +08:00
Chen Xin 9fe7b955e5 Fixed average pool layout infer 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-16 13:34:31 +08:00
meseraph 883334e1bb add rnn 2022-11-16 13:33:39 +08:00
Feiyue Chen 11fd278d7a Fixed BidirectionalSequenceLSTM bug 
Fixed input error of  the backward direction
Fixed golden error of unit test

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-16 13:31:23 +08:00
Kee 4db479ece4 Set RNN internal dtype 
Init RNN internal dtype to avoid the
internal FC OP to go to the CPU path

Type:Code Improvement

Signed-off-by: Kee <xuke537@hotmail.com>
 2022-11-14 09:39:27 +08:00
Chen Xin 6816a0188a Added minimum unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-11 18:03:46 +08:00
Chen Xin 8867c8de35 Fixed roi_align golden mismatch error 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-11 18:02:36 +08:00
Feiyue Chen ed162d0176 Update internal for 22Q3 release 
update internal to commit-id: e2b0fde631fce349e0e3ad42b2a4d40ce7634a97

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-24 15:34:53 +08:00
Chen Xin 3fed6d6757 fixed bug when broadcast dimensions is negative 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-10-08 21:42:02 +08:00
Feiyue Chen a038df2a84 added transpose_test from https://github.com/VeriSilicon/TIM-VX/issues/429 2022-10-08 14:47:07 +08:00
Chen Xin 20db77ee61 Added two cases in strided_slice 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-29 20:24:09 +08:00
Chen Xin 535c9da867 Fixed bug when input's index is not 0 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-28 16:48:16 +08:00
Chen Xin 4c6299e7fd Added two reduce layout infer unittest 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-28 09:37:38 +08:00
Chen Xin 72f2c5b69e Supported composed layout infer & added unit test 
Fixed fc layout infer in rnncell layout infer
 2022-09-26 14:29:46 +08:00
Feiyue Chen 1802e558ad modified cumsum header && resolve conflict in README.md 2022-09-26 14:27:48 +08:00
Feiyue Chen 264e491d2a added cumsum op & added handle api after BindInput 2022-09-26 14:27:48 +08:00
Feiyue Chen 9cb37b920f added MaxPool3d op 2022-09-26 13:32:56 +08:00
Feiyue Chen 8b8d09aea3 added Rcp op & modified test_utils 2022-09-22 12:15:02 +08:00
Feiyue Chen 1b07b022e2 added sign & softsign 2022-09-20 22:49:45 +08:00
Feiyue Chen f4d5e170de added & modified copyright of some files 2022-09-20 22:47:33 +08:00
Feiyue Chen 84b464ee8b Update README.md 2022-09-20 22:47:33 +08:00
Feiyue Chen 6099022f00 added Mod op & Mod unit test 2022-09-20 22:47:33 +08:00
Chen Xin 9b13b6f677 Replace name direct_map_op with builtin_op 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-19 10:21:19 +08:00
Feiyue Chen 113c3722cb supported int16 dfp quantization & added conv2d unit test 2022-09-15 22:15:22 +08:00
Feiyue Chen 95401036ab fixed some errs on gcc12 2022-09-15 21:26:43 +08:00
Chen Xin 6d9ed7b25b Disabled a conv3d case 
because of some branches are not fully supported

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-15 10:46:05 +08:00
Chen Xin 0bb547b8e4 disabled two Div cases 
int32 type not supported in branch 234062
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-06 23:58:03 +08:00
Chen Xin e62b62015d Added conv3d unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-06 11:45:24 +08:00
xiang.zhang e9771746ba Fix error in feature compatiable guard 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-09-05 15:05:50 +08:00
Chen Xin f348c8e36c disabled two not supported cases 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-05 14:52:59 +08:00
Sven 9de8df404c
Feat: disable maxpoolwithargmax2 feature if no low-level feature avaiable (#471) 
Convert operation list as compiler flags in cmake, when add new
operation in tim-vx, always check if the feature define is available or
not - so that tim-vx can compile with legacy ovxlib library.

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-09-01 18:56:49 +08:00
Chen Xin f6121140b0 Mapped unidirectional gru & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:27:05 +08:00
Chen Xin 58395cf7a7 Modified bidirectional_sequence_lstm golden accuracy 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:26:07 +08:00
root 80fed36ea3 Modified Div_int unit test golden 
Signed-off-by: root <root@DESKTOP-K365DSV.localdomain>
 2022-08-30 10:28:09 +08:00
Chen Xin 1c640c6f10 Mapped bidirectional lstm & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-22 10:42:05 +08:00
Kee 96d186c8d2 Set graph attributes when compile graph to binary 
Keep the same graph attributes as compile graph

Signed-off-by: Kee <xuke537@hotmail.com>
 2022-08-15 06:34:08 +08:00
Chen Xin 944fdfad8f Mapped GRUCell & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 20:34:19 +08:00
Chen Xin 03b5ec2d17 Added div int32 unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 14:37:34 +08:00
Tang a5ba633fe4 add readme for ovxlib_bin_build.sh 2022-08-08 16:52:45 +08:00
yuenan.li 9a28ff5758 Fix the build error for clang when export TIM_VX_ENABLE_PLATFORM=ON 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-08-08 16:50:25 +08:00
Chen Xin 3663a99e0f Fixed param compute bug for lrn 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-04 21:35:59 +08:00
ZhangXiang 6d47ee3ac1 Expose hw feature : isClOnly() 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-08-03 09:06:32 +08:00
Chen Xin 27b4298b29 Fixed quantize param in reduce_sum 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-29 11:12:09 +08:00
qin.chen 9ebddb5452 add op: maxpoolwithargmax2 and maxpoolgrad 2022-07-29 11:11:33 +08:00
qin.chen 84d76e5251 fixed: maxpoolwithargmax's output1 have wrong shape, internal id: I7d5aeab58038bacb73373a4ff4f48a12bb6441db 2022-07-29 11:11:33 +08:00
Antkillerfarm 32241dc4ad
Rename RoiAlign & RoiPool (#446) 2022-07-29 11:10:25 +08:00