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remove gen file in fpga

This commit is contained in:
colin 2022-02-27 04:49:27 +00:00
parent 1d1237c223
commit 94c99367ba
5 changed files with 1 additions and 156319 deletions
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1
VexRiscv/fpga/.gitignore vendored Normal file
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gen

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VexRiscv/fpga/gen/soc.json
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VexRiscv/fpga/gen/synth.log
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VexRiscv/fpga/gen/synth.v
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VexRiscv/fpga/gen/synth.ys
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read_verilog ../Murax.v
hierarchy -check -top Murax
synth -run coarse; opt -fine
write_verilog -noexpr -noattr gen/synth.v
synth_ecp5 -top Murax -json gen/soc.json