Commit Graph

11 Commits

Author SHA1 Message Date
Joseph Rahmeh 6b1e5ded3a Version 1.6 2020-05-15 11:28:59 -07:00
Olof Kindgren 63e74e2391 Add initial FuseSoC support
This adds support for using SweRV with FuseSoC. For SweRV itself, it allows linting with verilator running simulations with the provided testbench using most available simulators and doing synthesis for resource usage analysis with Vivado. It also allows SweRV to be integrated into FuseSoC-built SoCs, such as [SweRVolf](https://github.com/chipsalliance/Cores-SweRVolf)

**Quickstart**

1. Install [FuseSoC](https://github.com/olofk/fusesoc) and Verilator
2. Create an empty workspace directory. All subsequent commands are run from this directory
3. Add SweRV as FuseSoC library `fusesoc library add swerv https://github.com/chipsalliance/Cores-SweRV`
4. Run linting with Verilator `fusesoc run --target=lint chipsalliance.org:cores:SweRV_EH1`
5. Run testbench with default simulator (Verilator) `fusesoc run --target=sim chipsalliance.org:cores:SweRV_EH1`
6. Run testbench with another supported simulator (e.g. ModelSim) `fusesoc run --target=sim --tool=modelsim chipsalliance.org:cores:SweRV_EH1`
7. Run synthesis with Vivado `fusesoc run --target=synth chipsalliance.org:cores:SweRV_EH1`

* configs/swerv_config_gen.py is a wrapper around `configs/swerv.config` to dynamically create a SweRV configuration by setting parameters in the FuseSoC .core file
* swerv.core is the FuseSoC core description file
* tools/vivado.tcl marks `common_defines.vh` as a global include file when using Vivado
2020-02-24 21:28:54 +01:00
Joseph Rahmeh b65d4dd8f1 Version 1.5 2020-02-19 18:25:04 -08:00
Joseph Rahmeh 790c48cd0b Version 1.5 2020-02-19 18:24:28 -08:00
Joseph Rahmeh 3820e84e20 Move declarations to top of Verilog file to fix fpga compile issues. 2019-10-15 13:14:36 -07:00
Joseph Rahmeh 811e9c3d24 Change clock header instance name in beh_lib.sv 2019-09-04 14:39:10 -07:00
Joseph Rahmeh 4e161e6c3b Minor cleanup in config script. 2019-08-13 15:47:53 -07:00
Joseph Rahmeh d9bb036633 Updated hello world message. Updated last compilation time. 2019-08-13 12:57:04 -07:00
Joseph Rahmeh ac92841999 Adjust CSR MFDC reset value for the AXI bus. 2019-08-13 12:38:50 -07:00
Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
Joseph Rahmeh c0f7e509cc SweRV 1.1 2019-06-04 07:57:48 -07:00