18c8352c09
Add ram test and verilator in fpga DEMO.
2022-02-09 12:47:35 +00:00
3c3cfccfd5
add ram test.
2022-02-08 03:00:40 +00:00
a7ef641f0d
Refine io level
2022-02-07 13:34:50 +00:00
3405c88c9e
Correct blink and use sample blink code
2022-02-07 13:23:34 +00:00
3370d01917
Add verilator install method in readme.
2022-02-07 08:13:16 +00:00
3ba8533996
Add fpga
2022-02-02 03:43:53 +00:00
a15c797e93
add jtag to ESP32
2022-02-02 03:40:41 +00:00
853d12f17c
Init to abstract accelerator project
2022-02-02 03:34:37 +00:00
f299211d91
Refine readme for rocket tool build
2022-02-01 15:50:30 +00:00
d8c2a6861b
refine Readme for demo
2022-01-27 16:42:31 +08:00
Colin
3ed8011eaa
add jtag demo for GDB which openocd
2022-01-22 08:08:47 +00:00
Colin
5f80832b1a
add jtag demo and refine Makefile
2022-01-20 03:44:59 +00:00
Colin
a8fc3642ad
Add dpi of jtag
2022-01-19 12:45:38 +00:00
Colin
65f5085afa
refine makefile
2022-01-19 09:57:37 +00:00
Colin
9174bfe249
mv flist to soc folder
2022-01-17 12:18:33 +00:00
Colin
1437f0fcf3
move swerv config and json to soc
2022-01-17 12:14:05 +00:00
Colin
7aff1ae5f1
add soc for common test with soc.
2022-01-17 11:53:50 +00:00
Colin
3be1146718
refine define file build
2022-01-17 11:40:11 +00:00
Colin
1d8069026b
remove no use file in demo
2022-01-17 11:10:22 +00:00
Colin
2b298f0fff
rename test to demo
2022-01-17 06:43:14 +00:00
Colin
0eb74fdc10
refine test use function
2022-01-05 03:47:27 +00:00
Colin
6567357739
add llvm build flow from .c file
2022-01-04 12:39:14 +00:00
Colin
be63e84a1d
Add build from llvm
2021-12-17 13:29:59 +00:00
Colin
911f65874f
add test of verilator in one folder
2021-12-16 12:08:59 +00:00
87c23b9952
Merge pull request #101 from antmicro/fix-vivado-tcl
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Remove not existing file from vivado.tcl
2021-10-08 17:45:03 -04:00
f57cce19ff
Remove not existing file from vivado.tcl
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-08-27 15:27:02 +02:00
81bff1c0d7
reverting to 0242c9e for swerv_config_gen.py
2021-03-12 08:02:57 -05:00
d4e7b25f71
Merge pull request #93 from antmicro/variable-order-fix
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Declare variables before using them
Thank you for this update.
2021-02-19 15:03:43 -05:00
74a6bdb50d
Do not use variables before declaration
2021-02-17 17:09:35 +01:00
f3da044f15
Delete testbench/tests/cmark_dccm directory
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This directory is redundant due to the reworking of test flow in release 1.9
2021-02-16 08:56:23 -05:00
5e23462bd0
Update README.md
2021-02-03 13:26:41 -08:00
695883a674
Removed dead code.
2021-02-03 11:08:48 -08:00
0c92ea167b
Version 1.9
2021-02-03 07:07:10 -08:00
ec254f5491
Version 1.9.
2021-01-27 09:36:43 -08:00
bcb5b33726
Merge pull request #82 from chipsalliance/quartus_core_fix
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Only load Vivado TCL files when using Vivado
2021-01-21 17:59:41 -05:00
bb9f9ef37b
Merge pull request #89 from olofk/scan_mode
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Remove unused scan_mode input from dmi_wrapper.
We will be releasing some fixes shortly which will have this change too. Accepting your PR so as not hold up any progress.
2021-01-21 17:58:36 -05:00
bcf505751e
Remove unused scan_mode input from dmi_wrapper
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This causes the dmi wrapper from SweRV EH1 and SweRV EL2 to have
the same interface which makes it easier to use the two CPU cores
interchangeably in a design.
2021-01-18 10:15:08 +01:00
3918a8d345
Only load Vivado TCL files when using Vivado
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This prevents the vivado-specific TCL file to be loaded when using the synth target with other synthesis tools than vivado
2020-11-24 09:31:52 +01:00
7332edc0ad
Merge pull request #76 from olofk/snapshot_dir2
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Set snapshot dir to a known location in FuseSoC SweRV config generator
2020-09-24 10:26:32 -04:00
0242c9e6d2
Explicitly use python3
2020-09-24 15:24:30 +02:00
801d0f66f6
Set snapshot dir to a known location in FuseSoC SweRV config generator
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The previous fix for the FuseSoC SweRV config generator was not complete
2020-09-24 14:32:08 +02:00
1e8c6e3813
Merge pull request #75 from olofk/snapshot_dir
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Adapt FuseSoC SweRV config generator wrt new snapshot dir
2020-09-22 13:41:35 -04:00
2627ccc82b
Adapt FuseSoC SweRV config generator wrt new snapshot dir
2020-09-22 16:27:04 +02:00
f32b634c16
Updated per issue #70
2020-09-22 09:58:03 -04:00
3c50837a75
Update release-notes.md
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Minor corrections
2020-09-18 18:00:45 -07:00
e63dfe17d8
Updated version in swerv.core
2020-09-18 14:42:34 -07:00
d6024bcc6b
Updated branch number in README file.
2020-09-18 14:08:43 -07:00
d395a96492
Updated branch number in README file.
2020-09-18 14:03:24 -07:00
8caf5f69b0
Added testbench/hex directory.
2020-09-18 13:47:53 -07:00
95e9589446
Updated PRM.
2020-09-18 13:47:21 -07:00
colin
Colin
Ajay Nath
Kamil Rakoczy
Ajay Nath
Tomasz Gorochowik
Thomas Wicki
Joseph Rahmeh
Olof Kindgren