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9 Commits

Author SHA1 Message Date
Olof Kindgren bcf505751e Remove unused scan_mode input from dmi_wrapper 
This causes the dmi wrapper from SweRV EH1 and SweRV EL2 to have
the same interface which makes it easier to use the two CPU cores
interchangeably in a design.
 2021-01-18 10:15:08 +01:00
Joseph Rahmeh 5e613582c2 New branch: branch1.8 2020-09-18 13:34:02 -07:00
jrahmeh cb5a7a141d
Update dmi_jtag_to_core_sync.v 
Follow syntax used in internal repository.
 2020-02-24 15:00:46 -06:00
jrahmeh 2a1d9be0c2
Update dmi_jtag_to_core_sync.v 
Fixed incorrect syntax
 2020-02-24 14:52:54 -06:00
Joseph Rahmeh b65d4dd8f1 Version 1.5 2020-02-19 18:25:04 -08:00
Arup De aa2bc2269d Fixed FPGA build error 2019-12-06 09:50:38 -08:00
Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
 2019-08-07 17:04:48 -07:00
Joseph Rahmeh 0f3f246df5 Remove spurious carriage return characters. 2019-07-12 06:22:01 -07:00
Joseph Rahmeh c0f7e509cc SweRV 1.1 2019-06-04 07:57:48 -07:00