8caf5f69b0
Added testbench/hex directory.
2020-09-18 13:47:53 -07:00
5e613582c2
New branch: branch1.8
2020-09-18 13:34:02 -07:00
6b1e5ded3a
Version 1.6
2020-05-15 11:28:59 -07:00
ee77552301
Version 1.5
2020-02-19 18:57:15 -08:00
b65d4dd8f1
Version 1.5
2020-02-19 18:25:04 -08:00
790c48cd0b
Version 1.5
2020-02-19 18:24:28 -08:00
3820e84e20
Move declarations to top of Verilog file to fix fpga compile issues.
2019-10-15 13:14:36 -07:00
cf4d56c78c
Added basic commit register update trace in exec.log
2019-09-08 11:13:17 -04:00
b35d7e9e1b
Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.
2019-09-04 13:29:39 -07:00
d9bb036633
Updated hello world message. Updated last compilation time.
2019-08-13 12:57:04 -07:00
7ff8d7fb5a
Untabified files.
2019-08-13 12:48:48 -07:00
0dacc978da
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
...
not start an SB write access when sbreadonaddr/dbreadondata is set.
Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
8c413fd1e2
Removed invalid include statement.
2019-07-12 11:26:03 -07:00
e40f01e15d
Moved flist.questa to testbench directory.
2019-07-12 11:25:07 -07:00
0f3f246df5
Remove spurious carriage return characters.
2019-07-12 06:22:01 -07:00
412c128fb0
Removed duplicate declaration of finished for Verilator.
2019-06-20 09:50:50 -07:00
c0f7e509cc
SweRV 1.1
2019-06-04 07:57:48 -07:00
Joseph Rahmeh
Ajay Nath