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25 Commits

Author SHA1 Message Date
Olof Kindgren 6815b77864 Fix typo in swerv.config causing wrong unsets to be printed 
This is only for the summary of options. No functional change
 2020-09-25 12:04:05 +02:00
Ajay Nath e4a822bd50
Merge pull request #9 from olofk/mem_lib_fix 
Mem lib fix
 2020-09-24 20:14:24 -04:00
Olof Kindgren 958d280546 Explicitly use python3 everywhere 2020-09-24 16:18:27 +02:00
Olof Kindgren 025a720e35 Fix non-blocking assignment in mem_lib.sv 
A typo in mem_lib.sv caused suboptimal mapping which led to high
resource usage on FPGA targets.
 2020-09-24 16:16:03 +02:00
jrahmeh 4c5674ca35
Merge pull request #3 from olofk/corefixes 
Fix toplevel in FuseSoC core file
 2020-08-19 10:07:45 -05:00
Olof Kindgren b36d3bbff9 Fix toplevel in FuseSoC core file 2020-05-27 14:30:11 +00:00
Joseph Rahmeh a5a72bf84f Fixed file names. 2020-05-15 07:33:45 -07:00
Joseph Rahmeh c8b9057c8b Added hex data for sample programs. 2020-05-15 06:32:19 -07:00
Ajay Nath e1301d4d47 Added fpga_optimize help note top swerv.config 2020-03-30 17:55:40 -04:00
jrahmeh 188f57f72c
Removed duplicate header 2020-03-30 16:08:40 -05:00
Joseph Rahmeh e494ab6c9b Release 1.2 2020-03-30 14:00:19 -07:00
Joseph Rahmeh 062c27e9cb Updated PRM fo release 1.2 2020-03-30 07:24:39 -07:00
Joseph Rahmeh 179469ea5b Release 1.2 2020-03-27 13:38:09 -07:00
Joseph Rahmeh dfc027b4a5 Release 1.1 2020-03-05 13:47:00 -08:00
Joseph Rahmeh 5b42a1038a Renamed PRM file. 2020-03-05 12:53:19 -08:00
Joseph Rahmeh 1aec19e556 Release 1.1 2020-03-04 18:39:07 -08:00
Joseph Rahmeh baedad0741 Added new files for release 1.1 2020-03-04 18:37:08 -08:00
Joseph Rahmeh 1d2db09a2b Release 1.1 2020-03-04 15:36:01 -08:00
aprnath a49b298b4a
Merge pull request #2 from chipsalliance/fusesoc 
Add FuseSoC support for SweRV EL2
 2020-03-03 14:26:30 -05:00
Olof Kindgren a08b395d8c Add FuseSoC support for SweRV EL2 
This adds an initial FuseSoC core description file for SweRV EL2.

In addition to the core file there is also a python wrapper for
the core configuration (configs/swerv_config_gen.py) that is used
as a FuseSoC generator. There is also a tcl file (tools/vivado.tcl)
with Vivado-specific options that FuseSoC will pick up automatically
when Vivado is used.

It has been successfully tested in a modified SweRVolf SoC to boot
Zephyr OS in a Verilator simulation and on the Nexys A7 FPGA board.

TODO:

- Add target for running the bundled SweRV EL2 testbench
- Add Model/Questasim support
 2020-01-31 10:36:53 +01:00
Joseph Rahmeh cd8ec04439 Added .gitignore. 2020-01-24 06:57:16 -08:00
tmw-wdc 1cf874e09d Update RISC-V SweRV EL2 PRM.pdf 
Updated footer
 2020-01-23 16:42:59 -08:00
Joseph Rahmeh 7a48835c4e Initial checkin. 2020-01-22 14:22:50 -08:00
jrahmeh 83c5a4f97a
Update README.md 2020-01-09 16:16:59 -06:00
jrahmeh 25593b49dc
Initial commit 2020-01-09 16:16:40 -06:00