d86fef92e2
Enable gdb by openocd.
2022-03-08 09:18:19 +00:00
ddf80fde8d
Add jtag
2022-03-07 13:08:10 +00:00
7045b803ca
Merge pull request #26 from dawidzim/update_make_for_riviera
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Update Riviera-PRO makefile
2021-05-21 11:21:03 -04:00
92ec09ddad
remove -err VCP2694
2021-05-21 11:33:28 +02:00
59a46cea64
Updated README.md file.
2021-04-19 16:52:33 -07:00
5d11e392bd
Updated PRM for version 1.4.
2021-04-19 13:57:57 -07:00
5e9c9361e4
Removed dead code.
2021-04-19 13:04:49 -07:00
fb3354352b
Branch 1.4
2021-04-19 07:56:12 -07:00
9260b5567c
Merge pull request #20 from olofk/config_gen
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Update FuseSoC SweRV config generator
2021-01-15 10:26:44 -08:00
5672ff31b5
Update FuseSoC SweRV config generator
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Adapt swerv_config_gen.py to changes in the swerv.config script in
the SweRV EL2 1.3 release
2021-01-15 15:27:42 +01:00
ae8be27b34
Merge pull request #17 from danielmlynek/riviera_support_fixes
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Fixes in riviera support which was pushed onto 1.3 version
Apologies for the shoddy manual merge in 1.3.
2020-11-20 14:44:26 -05:00
9755d8f94a
Fixes in riviera support pushed into 1.3
2020-11-20 16:38:02 +01:00
ebfb8abf88
Branch 1.3
2020-11-17 11:14:35 -08:00
14b63d877f
Branch 1.3
2020-11-17 11:00:40 -08:00
068356d5da
Branch 1.3
2020-11-17 10:58:44 -08:00
2d26189faf
Branch 1.3
2020-11-17 10:25:18 -08:00
7570549cf7
Merge pull request #10 from olofk/unsets_typo
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Fix typo in swerv.config causing wrong unsets to be printed
2020-09-25 08:38:40 -04:00
6815b77864
Fix typo in swerv.config causing wrong unsets to be printed
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This is only for the summary of options. No functional change
2020-09-25 12:04:05 +02:00
e4a822bd50
Merge pull request #9 from olofk/mem_lib_fix
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Mem lib fix
2020-09-24 20:14:24 -04:00
958d280546
Explicitly use python3 everywhere
2020-09-24 16:18:27 +02:00
025a720e35
Fix non-blocking assignment in mem_lib.sv
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A typo in mem_lib.sv caused suboptimal mapping which led to high
resource usage on FPGA targets.
2020-09-24 16:16:03 +02:00
4c5674ca35
Merge pull request #3 from olofk/corefixes
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Fix toplevel in FuseSoC core file
2020-08-19 10:07:45 -05:00
b36d3bbff9
Fix toplevel in FuseSoC core file
2020-05-27 14:30:11 +00:00
a5a72bf84f
Fixed file names.
2020-05-15 07:33:45 -07:00
c8b9057c8b
Added hex data for sample programs.
2020-05-15 06:32:19 -07:00
e1301d4d47
Added fpga_optimize help note top swerv.config
2020-03-30 17:55:40 -04:00
188f57f72c
Removed duplicate header
2020-03-30 16:08:40 -05:00
e494ab6c9b
Release 1.2
2020-03-30 14:00:19 -07:00
062c27e9cb
Updated PRM fo release 1.2
2020-03-30 07:24:39 -07:00
179469ea5b
Release 1.2
2020-03-27 13:38:09 -07:00
dfc027b4a5
Release 1.1
2020-03-05 13:47:00 -08:00
5b42a1038a
Renamed PRM file.
2020-03-05 12:53:19 -08:00
1aec19e556
Release 1.1
2020-03-04 18:39:07 -08:00
baedad0741
Added new files for release 1.1
2020-03-04 18:37:08 -08:00
1d2db09a2b
Release 1.1
2020-03-04 15:36:01 -08:00
a49b298b4a
Merge pull request #2 from chipsalliance/fusesoc
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Add FuseSoC support for SweRV EL2
2020-03-03 14:26:30 -05:00
a08b395d8c
Add FuseSoC support for SweRV EL2
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This adds an initial FuseSoC core description file for SweRV EL2.
In addition to the core file there is also a python wrapper for
the core configuration (configs/swerv_config_gen.py) that is used
as a FuseSoC generator. There is also a tcl file (tools/vivado.tcl)
with Vivado-specific options that FuseSoC will pick up automatically
when Vivado is used.
It has been successfully tested in a modified SweRVolf SoC to boot
Zephyr OS in a Verilator simulation and on the Nexys A7 FPGA board.
TODO:
- Add target for running the bundled SweRV EL2 testbench
- Add Model/Questasim support
2020-01-31 10:36:53 +01:00
cd8ec04439
Added .gitignore.
2020-01-24 06:57:16 -08:00
1cf874e09d
Update RISC-V SweRV EL2 PRM.pdf
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Updated footer
2020-01-23 16:42:59 -08:00
7a48835c4e
Initial checkin.
2020-01-22 14:22:50 -08:00
83c5a4f97a
Update README.md
2020-01-09 16:16:59 -06:00
25593b49dc
Initial commit
2020-01-09 16:16:40 -06:00
colin
Ajay Nath
Dawid Zimonczyk
Joseph Rahmeh
Zvonimir Bandic
Olof Kindgren
Daniel Mlynek
jrahmeh
Ajay Nath
tmw-wdc