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605 Commits

Author SHA1 Message Date
colin.liang 8196dedc35 TTTT. 2023-01-12 15:38:54 +08:00
colin.liang b99c193120 Remove counter parameter. Default enable. 2023-01-10 20:52:25 +08:00
colin.liang f714dd5da4 Change stackpoint to h0001_0000. 2023-01-10 20:28:17 +08:00
colin.liang a015d7d595 Remove no use default config. 2023-01-10 19:59:13 +08:00
colin.liang d1b0213ff0 Default donot use compress isa. 2023-01-10 19:56:05 +08:00
colin.liang d4ce161c1c format testbench. 2023-01-10 15:44:16 +08:00
colin.liang 42e498aa28 mv from picorv to testbench 2023-01-10 15:43:08 +08:00
colin.liang 0e6103f51f Remove wb RAM. 2023-01-09 20:05:40 +08:00
colin.liang 6d34315889 remove unused picorv32. 2023-01-09 18:23:42 +08:00
colin.liang 3feacd84c4 Delete RISCV_FORMAL_ALTOPS. 2023-01-09 15:35:06 +08:00
colin.liang f02c0b23c4 Delete axi ez sp. 2023-01-09 15:33:37 +08:00
colin.liang c676992a07 Remove RISCV_FORMAL. 2023-01-09 13:26:32 +08:00
colin.liang 3bda5c9e63 Fix to run environment problem. 2023-01-07 19:37:25 +08:00
Claire Xen f00a88c36e
Merge pull request #209 from YosysHQ/micko/cleanups 
Cleanups
 2022-01-03 16:03:13 +01:00
Miodrag Milanovic e8dbd9ac6a Fix dhrystone 2021-12-27 11:09:39 +01:00
Miodrag Milanovic d330c1406b fix for check target 2021-12-27 10:52:12 +01:00
Miodrag Milanovic b08952b896 Fix gitignore 2021-12-27 10:18:51 +01:00
Miodrag Milanovic 0b87954437 Fix simulation 2021-12-27 10:18:30 +01:00
Claire Xen 1d9f5b7678
Merge pull request #166 from tommythorn/master 
Enable the use of 64-bit riscv tools
 2021-12-06 16:10:29 +01:00
Claire Xen 6b1397700f
Merge pull request #173 from tonymmm1/hx8kdemo-nextpnr 
changed hx8kdemo from arachne-pnr to nextpnr-ice40
 2021-12-06 16:09:28 +01:00
Claire Xen 354f65ab4a
Merge pull request #202 from osresearch/icebreaker-fast-mul 
picosoc: enable fast multiply option for icebreaker
 2021-12-06 16:09:00 +01:00
Miodrag Milanovic e8edf98772 add license file 2021-12-03 15:54:08 +01:00
Claire Xenia Wolf 100e421be0 Fix copyright info 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-02 15:59:12 +01:00
Trammell Hudson eeca10190b picosoc: enable fast multiply option for icebreaker 
This patch splits the picosoc's `ENABLE_MULDIV` paramter
into `ENABLE_MUL`, `ENABLE_DIV` and `ENABLE_FAST_MUL`,
and also enables the DSP-based fast multiplier for
the iCE40up5k icebreaker board.

Signed-off-by: Trammell Hudson <hudson@trmm.net>
 2021-09-02 16:35:38 +00:00
tonymmm1 8588576692 changed hx8kdemo from arachne-pnr to nextpnr-ice40 2020-08-09 20:58:19 -05:00
Tommy Thorn 2cce6f4e8b Enable the use of 64-bit riscv tools 
Many Linux distributions now include the tools for RISC-V (for example
Ubuntu 20.04 has gcc-riscv64-unknown-elf) but in order for

  make TOOLCHAIN_PREFIX=riscv64-unknown-elf-

to work we need to be explicit about compiling for 32-bit.
 2020-06-03 09:27:30 -07:00
Larry Doolittle f9b1beb4cf Make Makefile more flexible 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-27 17:23:45 +02:00
Larry Doolittle 59ef49564f Remove obsolete line from firmware/sections.lds 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-23 18:01:24 +02:00
Larry Doolittle 25c58766c3 Disable RVC in tests/jal.S and tests/jalr.S 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-23 18:00:51 +02:00
Larry Doolittle e03c43ea43 Add plusargs support to testbench.cc 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-23 18:00:16 +02:00
Larry Doolittle 9129d18bf5 Cleanup whitespaces 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-23 17:59:17 +02:00
Claire Wolf 409d0dfd67
Merge pull request #145 from Novakov/patch-1 
spimemio documentation: read latency reset value
 2020-04-22 17:32:19 +02:00
Claire Wolf fe1ee2c739
Merge pull request #152 from RolinBert/master 
Fix #151 (missing irqs)
 2020-04-22 17:31:29 +02:00
Claire Wolf 65e72ea49e
Merge pull request #156 from dehann/patch-1 
fix readme icebreaker links
 2020-04-22 17:25:28 +02:00
Claire Wolf fb34c8aca9
Merge pull request #148 from splinedrive/disable_memory_test 
Workarround: Disable cmd_memtest() when starting firmware.
 2020-04-22 17:25:05 +02:00
Claire Wolf 824a5c8011
Merge pull request #158 from rxrbln/uart 
added default clk divider parameter to simpleuart
 2020-04-15 18:49:23 +02:00
René Rebe a7ff70dfb4 added default clk divider parameter to simpleuart 2020-04-15 13:25:57 +02:00
dehann b428e843cd
fix icebreaker links 2020-04-12 14:42:45 -04:00
Robert Korn fac01cee1c - fix missing brackets 2020-03-30 19:00:28 +02:00
Robert Korn 258d63d476 - fix missed timer interrupts, 
when another interrupt activates shortly before
 2020-03-27 07:26:48 +01:00
Hirosh Dabui 1b6821d1a1 Workarround: Disable cmd_memtest() when starting firmware. 
It destroys bss and data section memory.
You are not able to use static or global vars.
 2020-01-27 02:19:56 +01:00
Maciej T. Nowak 0201e8ff02
spimemio documentation: read latency reset value 
According to c06ba38113/picosoc/spimemio.v (L111) the reset value for `Read latency (dummy) cycles` is 8 cycles, not 0.
 2020-01-03 21:57:19 +01:00
Clifford Wolf e308982e18
Merge pull request #141 from rxrbln/master 
added CROSS prefix and CFLAGS to the picsoc/Makefile
 2019-11-18 14:21:10 +01:00
René Rebe 1e24e99970 added CROSS prefix and CFLAGS to the picsoc/Makefile 
so one can run it with other toolchains, e.g.
CROSS=riscv64-t2-linux-gnu- CFLAGS=-mabi=ilp32, too
 2019-11-14 12:31:20 +01:00
Clifford Wolf 46aa89c13f
Merge pull request #138 from pcotret/patch-1 
Short modification in the error string
 2019-10-31 11:25:37 +01:00
Pascal Cotret 415382761c
Short modification in the error string 2019-10-29 16:42:24 +01:00
Clifford Wolf 77277a0d32 Fix typo, closes #136 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-25 11:28:08 +02:00
Clifford Wolf 3f9b5048bc Fix initialization of "irq" in verilog testbench 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-22 13:59:43 +02:00
Clifford Wolf 881f928e05 Improve showtrace.py (and fix for new binutils) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-21 13:19:15 +02:00
Clifford Wolf 392ee1dd91 Improve test firmware, increase testbench memory size to 128kB 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-12 10:50:45 +02:00