Clifford Wolf
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d4331491a8
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Test firmware refactoring
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2015-06-26 23:15:30 +02:00 |
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Clifford Wolf
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f0b824ad9a
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Minor README changes
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2015-06-26 16:15:39 +02:00 |
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Clifford Wolf
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c06286423b
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Added build instructions for RV32I toolchain
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2015-06-26 13:53:43 +02:00 |
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Clifford Wolf
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f87d81287c
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More README changes
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2015-06-26 11:01:34 +02:00 |
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Clifford Wolf
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266ff03539
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Minor README changes
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2015-06-26 10:51:15 +02:00 |
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Clifford Wolf
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1a664f9b97
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Changed chip package in vivado examples
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2015-06-26 10:46:51 +02:00 |
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Clifford Wolf
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5d4ce82050
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Implemented waitirq instruction
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2015-06-26 10:39:08 +02:00 |
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Clifford Wolf
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9a4a06d981
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Refactoring of IRQ handling
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2015-06-26 10:03:37 +02:00 |
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Clifford Wolf
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9d26ebcf58
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Improvements in README.md
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2015-06-25 14:14:07 +02:00 |
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Clifford Wolf
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23b700cf73
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Added basic IRQ support
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2015-06-25 14:08:39 +02:00 |
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Clifford Wolf
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982e5cc600
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Added simple icestorm script (not a real example yet)
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2015-06-22 11:35:48 +02:00 |
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Clifford Wolf
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8590c7d2a8
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Updated Vivado SoC example
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2015-06-10 16:48:06 +02:00 |
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Clifford Wolf
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26127b45de
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Makefile for Vivado scripts
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2015-06-09 12:45:45 +02:00 |
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Clifford Wolf
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b4b1d03b1c
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More Todos
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2015-06-09 10:01:00 +02:00 |
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Clifford Wolf
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bb7f500489
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Removed unnecessary "jal" complexity
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2015-06-09 07:40:30 +02:00 |
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Clifford Wolf
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0257d2cb08
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Small improvements in vivado_soc demo
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2015-06-08 19:58:28 +02:00 |
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Clifford Wolf
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072e5ca2c5
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Added osu018 yosys synthesis script
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2015-06-08 09:31:56 +02:00 |
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Clifford Wolf
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a9532f81ed
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Refactored instruction decoder
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2015-06-08 09:08:19 +02:00 |
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Clifford Wolf
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32208c0b70
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Improved timing for "decoded_imm_uj"
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2015-06-07 22:50:49 +02:00 |
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Clifford Wolf
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06ba3a1a57
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README Updates
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2015-06-07 20:59:20 +02:00 |
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Clifford Wolf
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34d9dea8c7
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Added support for dual-port register file
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2015-06-07 20:53:19 +02:00 |
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Clifford Wolf
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60867e10a9
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minor optimizations
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2015-06-07 20:08:04 +02:00 |
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Clifford Wolf
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8e3e0bfba0
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Improved "decoder_trigger" handling
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2015-06-07 19:49:38 +02:00 |
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Clifford Wolf
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bbbcea2faa
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Added look-ahead write interface
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2015-06-07 12:11:20 +02:00 |
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Clifford Wolf
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e84f044bc5
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Major redesign of main FSM
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2015-06-07 11:49:47 +02:00 |
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Clifford Wolf
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491cd5e15d
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Using libc assembler code in dhrystone stdlib.c
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2015-06-07 07:29:13 +02:00 |
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Clifford Wolf
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44ea992fed
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Updated CPI table in README
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2015-06-06 21:43:33 +02:00 |
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Clifford Wolf
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90ff3380a4
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Updated README
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2015-06-06 21:27:58 +02:00 |
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Clifford Wolf
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2107a328c4
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Added insn timing hack to dryhstone testbench
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2015-06-06 21:27:07 +02:00 |
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Clifford Wolf
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bc8ffd2ecb
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Added memory "look-ahead" read interface
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2015-06-06 20:50:53 +02:00 |
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Clifford Wolf
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9df9d7ff90
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Improved Xilinx example
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2015-06-06 20:14:58 +02:00 |
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Clifford Wolf
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abe0465753
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Faster memory model in dhrystone testbench
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2015-06-06 19:35:07 +02:00 |
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Clifford Wolf
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c55d537401
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Improved AXI tests
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2015-06-06 19:22:28 +02:00 |
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Clifford Wolf
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f9ae73066b
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Added license info to README
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2015-06-06 17:24:11 +02:00 |
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Clifford Wolf
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7fd24a96b2
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Improved AXI Interface Testbench
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2015-06-06 17:15:09 +02:00 |
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Clifford Wolf
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77ba5a1897
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Initial import
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2015-06-06 14:14:32 +02:00 |