Clifford Wolf
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9d5f8ad8e6
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Towards compressed ISA support
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2015-11-19 04:02:00 +01:00 |
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Clifford Wolf
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c4e711209c
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Towards compressed ISA support
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2015-11-18 19:23:11 +01:00 |
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Clifford Wolf
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3aed9f7c65
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Towards compressed ISA support
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2015-11-18 15:55:29 +01:00 |
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Clifford Wolf
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8174d8fb7e
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Towards compressed ISA support
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2015-11-15 23:24:38 +01:00 |
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Clifford Wolf
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bfd2a4e0fa
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Towards compressed ISA support
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2015-11-15 16:04:04 +01:00 |
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Clifford Wolf
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bf4b0f3a63
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Towards compressed ISA support
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2015-11-14 19:22:00 +01:00 |
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Clifford Wolf
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60b9216856
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Towards compressed ISA support
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2015-11-14 14:11:21 +01:00 |
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Clifford Wolf
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db26b51afe
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Towards compressed ISA support
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2015-11-13 14:16:32 +01:00 |
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Clifford Wolf
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8eaeebf486
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Progress in "make check"
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2015-10-15 15:45:19 +02:00 |
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Clifford Wolf
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07f28068f6
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Added "make check"
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2015-10-14 23:26:04 +02:00 |
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Clifford Wolf
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16f97a86a1
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Reset bugfix (bug found via scripts/smt2-bmc/mem_equiv.*)
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2015-08-13 13:30:21 +02:00 |
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Clifford Wolf
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bf7f984d42
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Refactoring of TWO_CYCLE_ALU
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2015-07-08 23:15:14 +02:00 |
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Clifford Wolf
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dd30b57ea6
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Added TWO_CYCLE_ALU parameter
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2015-07-08 20:17:03 +02:00 |
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Clifford Wolf
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b6c4c2eeb9
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Added TWO_CYCLE_COMPARE
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2015-07-07 22:51:52 +02:00 |
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Clifford Wolf
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9c028fc965
|
Added missing LD_RS1 debug statements
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2015-07-02 14:51:28 +02:00 |
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Clifford Wolf
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ab503d5756
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Being more aggressive with parallel cases
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2015-07-02 12:55:05 +02:00 |
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Clifford Wolf
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c10125eb5c
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Added TWO_STAGE_SHIFT parameter
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2015-07-02 12:29:06 +02:00 |
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Clifford Wolf
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853ce91300
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Added `debug macro
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2015-07-02 12:17:45 +02:00 |
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Clifford Wolf
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c48a3b2434
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Removed trailing whitespaces
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2015-07-02 10:49:35 +02:00 |
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Clifford Wolf
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34193bf9df
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Added CATCH_MISALIGN and CATCH_ILLINSN
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2015-07-01 21:20:51 +02:00 |
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Clifford Wolf
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f6fe27ecbf
|
After some profiling: one-hot FSM encoding
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2015-07-01 21:20:31 +02:00 |
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Clifford Wolf
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4a9fda0737
|
Improvements in PCPI MUL core
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2015-06-30 16:51:26 +02:00 |
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Clifford Wolf
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7417a3e249
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Added LATCHED_IRQ parameter
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2015-06-29 07:54:47 +02:00 |
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Clifford Wolf
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46026ba985
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Added ENABLE_IRQ_QREGS and ENABLE_IRQ_TIMER
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2015-06-28 22:09:51 +02:00 |
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Clifford Wolf
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21157b8f1d
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Cleanups in PCPI interface
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2015-06-28 15:41:55 +02:00 |
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Clifford Wolf
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b076d72806
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Fixed PCPI instr prefetching
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2015-06-28 14:51:53 +02:00 |
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Clifford Wolf
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1f99de5117
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Improvements in picorv32_pcpi_mul
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2015-06-28 13:07:50 +02:00 |
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Clifford Wolf
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4c15e05298
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Moved ENABLE_MUL from picorv32_axi to picorv32
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2015-06-28 12:19:49 +02:00 |
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Clifford Wolf
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034e1a6af7
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Added PCPI to picorv32_axi
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2015-06-27 23:54:11 +02:00 |
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Clifford Wolf
|
7d1a484812
|
Implemented picorv32_pcpi_mul
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2015-06-27 23:53:51 +02:00 |
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Clifford Wolf
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dd8ed3c877
|
Added pcpi_wait interface
|
2015-06-26 23:48:50 +02:00 |
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Clifford Wolf
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0be990bd04
|
Added Pico Co-Processor Interface (PCPI)
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2015-06-26 23:15:35 +02:00 |
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Clifford Wolf
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5d4ce82050
|
Implemented waitirq instruction
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2015-06-26 10:39:08 +02:00 |
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Clifford Wolf
|
9a4a06d981
|
Refactoring of IRQ handling
|
2015-06-26 10:03:37 +02:00 |
|
Clifford Wolf
|
23b700cf73
|
Added basic IRQ support
|
2015-06-25 14:08:39 +02:00 |
|
Clifford Wolf
|
bb7f500489
|
Removed unnecessary "jal" complexity
|
2015-06-09 07:40:30 +02:00 |
|
Clifford Wolf
|
a9532f81ed
|
Refactored instruction decoder
|
2015-06-08 09:08:19 +02:00 |
|
Clifford Wolf
|
32208c0b70
|
Improved timing for "decoded_imm_uj"
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2015-06-07 22:50:49 +02:00 |
|
Clifford Wolf
|
34d9dea8c7
|
Added support for dual-port register file
|
2015-06-07 20:53:19 +02:00 |
|
Clifford Wolf
|
60867e10a9
|
minor optimizations
|
2015-06-07 20:08:04 +02:00 |
|
Clifford Wolf
|
8e3e0bfba0
|
Improved "decoder_trigger" handling
|
2015-06-07 19:49:38 +02:00 |
|
Clifford Wolf
|
bbbcea2faa
|
Added look-ahead write interface
|
2015-06-07 12:11:20 +02:00 |
|
Clifford Wolf
|
e84f044bc5
|
Major redesign of main FSM
|
2015-06-07 11:49:47 +02:00 |
|
Clifford Wolf
|
bc8ffd2ecb
|
Added memory "look-ahead" read interface
|
2015-06-06 20:50:53 +02:00 |
|
Clifford Wolf
|
7fd24a96b2
|
Improved AXI Interface Testbench
|
2015-06-06 17:15:09 +02:00 |
|
Clifford Wolf
|
77ba5a1897
|
Initial import
|
2015-06-06 14:14:32 +02:00 |