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169 Commits

Author SHA1 Message Date
colin.liang 2b3f3d3f3d Move debug from core to test bench. 2023-01-13 16:11:36 +08:00
colin.liang 361dba595d remove compressed_instr. 2023-01-12 19:55:50 +08:00
colin.liang 6e318265dc format code. 2023-01-12 19:00:41 +08:00
colin.liang 2d6b66d3b4 remove BARREL_SHIFTER. 2023-01-12 17:48:48 +08:00
colin.liang 3cfab6b748 remove TWO_STAGE_SHIFT. 2023-01-12 17:36:57 +08:00
colin.liang b5edff85f7 Remove TWO_CYCLE_COMPARE. 2023-01-12 17:35:47 +08:00
colin.liang bb0bf253eb remove TWO_CYCLE_ALU. 2023-01-12 17:31:14 +08:00
colin.liang 4beed17d0a Format code. 2023-01-12 17:22:59 +08:00
colin.liang 665f26dc63 remove unsed. 2023-01-12 17:09:59 +08:00
colin.liang 1436980611 remove WITH_PCPI. 2023-01-12 17:07:04 +08:00
colin.liang 92b7265264 Remote unuse fast mul code. 2023-01-12 17:04:17 +08:00
colin.liang 9adf1c0029 Remove Config of IRQ, Use reg module from latch. 2023-01-12 17:02:34 +08:00
colin.liang 9c0d7d7593 Remove MUL DIV config paremeter. 2023-01-12 16:27:05 +08:00
colin.liang af85947a58 Remote ENABLE_REGS_DUALPORT and init reg zero. 2023-01-12 16:09:10 +08:00
colin.liang 8b3d3390f5 Remove CATCH_MISALIGN CATCH_ILLINSN. 2023-01-12 16:05:34 +08:00
colin.liang d9e14153fc Remote COMPOSE_ISA support. 2023-01-12 15:58:11 +08:00
colin.liang b99c193120 Remove counter parameter. Default enable. 2023-01-10 20:52:25 +08:00
colin.liang 42e498aa28 mv from picorv to testbench 2023-01-10 15:43:08 +08:00
colin.liang 0e6103f51f Remove wb RAM. 2023-01-09 20:05:40 +08:00
colin.liang 3feacd84c4 Delete RISCV_FORMAL_ALTOPS. 2023-01-09 15:35:06 +08:00
colin.liang f02c0b23c4 Delete axi ez sp. 2023-01-09 15:33:37 +08:00
colin.liang c676992a07 Remove RISCV_FORMAL. 2023-01-09 13:26:32 +08:00
Claire Xenia Wolf 100e421be0 Fix copyright info 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-02 15:59:12 +01:00
Robert Korn fac01cee1c - fix missing brackets 2020-03-30 19:00:28 +02:00
Robert Korn 258d63d476 - fix missed timer interrupts, 
when another interrupt activates shortly before
 2020-03-27 07:26:48 +01:00
Clifford Wolf e6779ba52b Disable verilator warnings, fixes #128 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 15:16:06 +02:00
Clifford Wolf d046cbfa49 Add PICORV32_TESTBUG_nnn ifdefs for testing purposes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-30 11:30:18 +02:00
Clifford Wolf 18cd609853 Add rvfi_ixl 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 00:07:16 +02:00
Clifford Wolf e0baf2e0bd Add RVFI CSRs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 00:04:37 +02:00
Clifford Wolf 6d145b708d Rename decoded_imm_uj to decoded_imm_j 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 14:29:27 -08:00
Clifford Wolf 23d7bbdc8b Add rvfi_mode (set to constant 3 = M-mode) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-31 12:21:01 +02:00
Clifford Wolf ed69f9e451 Update riscv-formal altops bitmasks 2017-10-07 01:24:59 +02:00
Clifford Wolf 7b6aa21f34 Fix bug in picorv32_pcpi_div, Add RISCV_FORMAL_ALTOPS support 2017-10-06 17:33:44 +02:00
Clifford Wolf ad08edd2e5 Add PICORV32_REGS mechanism for ASIC sram instantiation 2017-10-01 15:45:46 +02:00
Clifford Wolf 1c889ee3b5 Silenced some warnings when ENABLE_MUL but not ENABLE_PCPI 2017-09-22 04:50:48 +02:00
Clifford Wolf 8db3073ff9 Add correct interupt handling in RVFI trace 2017-09-13 18:45:17 +02:00
Clifford Wolf 9fca5934aa Add rvfi_halt and rvfi_intr to picorv32_axi and picorv32_wb 2017-09-13 18:44:57 +02:00
Clifford Wolf 13f93b7000 Revert "Fix RISCV_FORMAL_BLACKBOX_REGS (broke liveness on branch ops)" 
This reverts commit 624bc05f98.
 2017-09-13 02:24:15 +02:00
Clifford Wolf 624bc05f98 Fix RISCV_FORMAL_BLACKBOX_REGS (broke liveness on branch ops) 2017-09-12 22:46:25 +02:00
Clifford Wolf cd72560937 Update rvfi_order according to current rvfi spec 2017-09-05 01:10:04 +02:00
Clifford Wolf f99cd747da Suppress writes to cpuregs[0] to prevent confusion 2017-07-14 11:20:55 +02:00
Larry Doolittle c9de8001fe Remove some trailing whitespace 2017-06-13 13:22:25 +02:00
Clifford Wolf 45b80f985a Add rvfi_halt and rvfi_intr ports 2017-06-06 20:27:45 +02:00
Clifford Wolf f295b900bc Add RVFI to AXI and WB wrappers modules, Add RVFI monitor support to test bench 2017-05-27 19:58:44 +02:00
Clifford Wolf bb9ebeb9e3 Fixed jalr, c_jalr, and c_jr insns (bug discovered by riscv-formal) 2017-05-18 17:19:08 +02:00
Clifford Wolf 436544ccab Fix decoding of C.ADDI instruction 
See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/mr3H6S6IIts
for discussion. There was a bug in the ISA manual.
 2017-05-13 12:28:54 +02:00
Clifford Wolf cd30db3425 Add riscv-formal alu/regs blackboxing 2017-05-11 00:13:01 +02:00
Clifford Wolf bf9687028d Fix decoding of illegal/reserved opcodes as other valid opcodes 2017-05-07 21:13:46 +02:00
Antony Pavlov 7c852571f0 testbench_wb.v: unify verbose output with axi testbench 
Unification of testbench output makes it possible to use the diff
utility for comparing testbench instruction traces.

Alas the testbench and testbench_wb traces are differ
because of interrupts, e.g.

    picorv32$ make testbench_wb.vvp
    iverilog -o testbench_wb.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench_wb.v picorv32.v
    chmod -x testbench_wb.vvp
    picorv32$ make testbench.vvp
    iverilog -o testbench.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench.v picorv32.v
    chmod -x testbench.vvp
    picorv32$ vvp -N testbench_wb.vvp +verbose | head -n 856 > /tmp/testbench_wb.log
    picorv32$ vvp -N testbench.vvp +verbose | head -n 856 > /tmp/testbench.log
    picorv32$ diff -u /tmp/testbench.log /tmp/testbench_wb.log
    --- /tmp/testbench.log  2017-04-06 06:56:06.079804549 +0300
    +++ /tmp/testbench_wb.log       2017-04-06 06:55:58.763485130 +0300
    @@ -850,7 +850,7 @@
     RD: ADDR=000056a0 DATA=00000013 INSN
     RD: ADDR=000056a4 DATA=fff00113 INSN
     RD: ADDR=000056a8 DATA=00000013 INSN
    -RD: ADDR=000056ac DATA=14208463 INSN  <--- testbench: no interrupt
    -RD: ADDR=000056b0 DATA=00120213 INSN
    -RD: ADDR=000056b4 DATA=00200293 INSN
    -RD: ADDR=000056b8 DATA=fe5212e3 INSN
    +RD: ADDR=00000010 DATA=0200a10b INSN  <--- testbench_wb: interrupt
    +RD: ADDR=00000014 DATA=0201218b INSN
    +RD: ADDR=00000018 DATA=000000b7 INSN
    +RD: ADDR=0000001c DATA=16008093 INSN

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-04-06 06:56:39 +03:00
Clifford Wolf 3495604877 Fix indenting in wishbone code 2017-03-14 11:51:09 +01:00