Clifford Wolf
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3495604877
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Fix indenting in wishbone code
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2017-03-14 11:51:09 +01:00 |
Antony Pavlov
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e59fa1dfb2
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WIP: add WISHBONE interconnect support
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
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2017-03-14 09:37:04 +03:00 |
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Clifford Wolf
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f33ddd3654
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Fix in rvfi_mem_ handling (when compressed isa is enabled)
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2017-02-27 14:21:42 +01:00 |
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Clifford Wolf
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aaa9e25756
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Add DEBUGNETS debug flag
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2017-02-26 16:56:13 +01:00 |
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Clifford Wolf
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c7cc32ed95
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Fix verilog code for modelsim
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2017-02-17 15:23:58 +01:00 |
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Clifford Wolf
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e4312b0fab
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Fix "mem_xfer is used before its declaration" warning
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2017-02-11 12:52:18 +01:00 |
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Clifford Wolf
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a2107ed4ff
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Rename RVFI ports
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2017-01-27 16:12:02 +01:00 |
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Clifford Wolf
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f975ce1e45
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Fix picorv32_axi STACKADDR default value
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2017-01-15 20:34:19 +01:00 |
Oguz Meteer
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510d4de1b1
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Add STACKADDR parameter to picorv32_axi module
Signed-off-by: Oguz Meteer <info@guztech.nl>
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2017-01-15 14:49:01 +01:00 |
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Clifford Wolf
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f5d146c2f1
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Added rvfi_mem interface
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2016-12-20 11:49:09 +01:00 |
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Clifford Wolf
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ef86b30b25
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Fixed some linter warnings in picorv32.v
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2016-12-15 14:03:27 +01:00 |
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Clifford Wolf
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72d6f6f72d
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Added rvfi_post_trap
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2016-12-13 17:13:53 +01:00 |
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Clifford Wolf
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54a8e4b311
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Fixed catching jumps to misaligned insn
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2016-11-29 18:36:05 +01:00 |
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Clifford Wolf
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17c7da49f4
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Renamed rvfi_opcode to rvfi_insn
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2016-11-28 14:56:29 +01:00 |
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Clifford Wolf
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7fc2cbd72a
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More RVFI bugfixes
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2016-11-27 13:46:43 +01:00 |
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Clifford Wolf
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fd38f876e1
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Minor RVFI bugfix
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2016-11-24 15:23:33 +01:00 |
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Clifford Wolf
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117586ff19
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Added RISC-V Formal Interfcae (RVFI)
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2016-11-23 03:02:02 +01:00 |
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Clifford Wolf
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f82af97595
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Another bugfix regarding compressed ISA and unaligned insns
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2016-11-18 15:36:59 +01:00 |
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Clifford Wolf
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4101cfe810
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Fixed the nontrivial compressed ISA bug found by tracecmp2
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2016-09-16 13:15:21 +02:00 |
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Clifford Wolf
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c209c016b3
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More fixes related to assertpmux checks
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2016-09-13 23:21:31 +02:00 |
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Clifford Wolf
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5bea3f9917
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Added more asserts for the memory interface
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2016-09-13 19:34:14 +02:00 |
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Clifford Wolf
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2f3e3a6910
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Merge pull request #21 from wallclimber21/mem_wdata
Only clock mem_wdata when necesssary
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2016-09-08 09:42:51 +02:00 |
Tom Verbeure
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38a760daf8
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Fix tabs
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2016-09-07 20:34:28 -07:00 |
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Tom Verbeure
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80aa70ec2e
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Only clock mem_wdata when necessary
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2016-09-07 20:32:32 -07:00 |
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Clifford Wolf
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44d6feba2a
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Using assertpmux in "make check"
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2016-09-07 12:40:19 +02:00 |
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Clifford Wolf
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da37498191
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Two minor bugfixes
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2016-09-06 19:58:03 +02:00 |
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Clifford Wolf
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7f946d0f84
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Added misisng MUL_CLKGATE stage
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2016-09-06 01:02:12 +02:00 |
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Clifford Wolf
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5fdee952c9
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Added picorv32_pcpi_fast_mul MUL_CLKGATE
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2016-09-05 22:37:52 +02:00 |
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Clifford Wolf
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e45cc362a7
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More picorv32_pcpi_mul timing improvements
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2016-09-04 18:34:11 +02:00 |
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Clifford Wolf
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e91c1422a2
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Added optional FFs to picorv32_pcpi_fast_mul
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2016-09-04 12:44:12 +02:00 |
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Clifford Wolf
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d5b7e9e175
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Minor bugfix/cleanup (mostly for formal verification)
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2016-09-03 14:40:13 +02:00 |
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Clifford Wolf
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c9519df01b
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Moved cpuregs read/write to extra always blocks
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2016-08-31 11:50:07 +02:00 |
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Clifford Wolf
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82d837bf96
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Be more explicit about single register file write port
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2016-08-31 00:08:33 +02:00 |
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Clifford Wolf
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bfba9b3eb3
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Bugfix in picorv32_pcpi_fast_mul
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2016-08-30 11:14:46 +02:00 |
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Clifford Wolf
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b9ed4364d4
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Merge branch 'fast_mul_opt' of https://github.com/wallclimber21/picorv32
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2016-08-30 11:12:42 +02:00 |
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Clifford Wolf
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cefe09b8d4
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Minor fixes/cleanups in mul reset logic
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2016-08-30 11:12:16 +02:00 |
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Tom Verbeure
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9201bff2ef
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Reduce rs1, rs2 from 64 to 33 bits to make life for synthesis tools easier.
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2016-08-29 18:00:49 -07:00 |
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Clifford Wolf
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a6210c06d4
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Added picorv32_pcpi_fast_mul core
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2016-08-29 23:38:05 +02:00 |
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Clifford Wolf
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90070736d6
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More asserts
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2016-08-29 22:44:15 +02:00 |
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Clifford Wolf
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28fe45ffe9
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Added more asserts to picorv32, more smtbmc examples
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2016-08-29 17:23:00 +02:00 |
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Clifford Wolf
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72158ba4a5
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Some minor cleanups
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2016-08-26 23:56:04 +02:00 |
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Clifford Wolf
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d1d3c3c5e1
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Added next gen yosys-smtbmc verification scripts
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2016-08-26 23:39:39 +02:00 |
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Clifford Wolf
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98d248d2c2
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Finalized tracer support
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2016-08-26 14:54:27 +02:00 |
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Clifford Wolf
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7094e61af7
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Added tracer support (under construction)
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2016-08-25 14:15:42 +02:00 |
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Clifford Wolf
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8043c90a04
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Added REGS_INIT_ZERO parameter
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2016-08-24 15:20:23 +02:00 |
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Clifford Wolf
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288a043aca
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Fixed use-before-declaration problem with VCS
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2016-06-09 11:57:23 +02:00 |
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Clifford Wolf
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bf062e39ac
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Added STACKADDR parameter
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2016-06-07 17:05:02 +02:00 |
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Clifford Wolf
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f4bb91b060
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RISC-V ISA 2.1 now calls "sbreak" officially "ebreak"
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2016-06-06 10:46:52 +02:00 |
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Clifford Wolf
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490a734519
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Encode in q0 LSB if interrupted instruction is compressed
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2016-06-01 12:39:00 +02:00 |
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Clifford Wolf
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fd18475e23
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Do not wait for PCPI core when handling SCALL and SBREAK
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2016-06-01 11:57:04 +02:00 |