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86 Commits

Author SHA1 Message Date
Clifford Wolf 7094e61af7 Added tracer support (under construction) 2016-08-25 14:15:42 +02:00
Clifford Wolf bec8d6a6b9 Fixed "make check" for new yosys-smtbmc cmdline 2016-08-20 19:18:49 +02:00
Clifford Wolf 22d73aafed Updated riscv-gnu-toolchain to git rev 7e48594 2016-08-17 01:06:10 +02:00
Clifford Wolf 30e815d104 Updated riscv-gnu-toolchain version to git rev 13f52d2 (2016-05-31) 2016-05-31 16:21:24 +02:00
Clifford Wolf 88299374cf Updated riscv-gnu-toolchain to 34db4e0 (now using gcc 6.1.0) 2016-05-05 12:06:29 +02:00
Clifford Wolf 6c69b3812e Using .vvp instead of .exe for iverilog executables 2016-05-04 08:57:16 +02:00
Clifford Wolf 8d453a1dd4 Building the tools in sequence is much faster 2016-04-11 22:54:15 +02:00
Clifford Wolf 5d422d7637 Added "make build-tools" 2016-04-11 12:46:29 +02:00
Clifford Wolf bc85a4c110 Updated riscv-gnu-toolchain (c.addi16sp bugfix) 2016-04-10 12:03:09 +02:00
Clifford Wolf df7f5915d7 Added documentation for COMPRESSED_ISA parameter 2016-04-09 14:35:17 +02:00
Clifford Wolf 36cdf83b3f Added "make clean" handling of riscv-gnu-toolchain-riscv32* directories 2016-04-09 12:51:50 +02:00
Clifford Wolf 579b60aef9 Added "make build-riscv32i-tools" and friends 2016-04-09 12:29:19 +02:00
Clifford Wolf 714f7d9cfa Merged axi4_memory.v and picorv32_wrapper.v back into testbench.v 2016-03-02 12:50:52 +01:00
Olof Kindgren 9591ae9f7d Split out verilator-incompatible code to top-level testbench 
Verilator doesn't handle verilog code that deals with time, such
as delayed signals or the repeat task. Clock and reset generation
are therefore moved to a separate file that can be replaced by
a verilator module. VCD generation is also affected by this.
 2016-02-18 22:47:15 +01:00
Olof Kindgren 8343315aa7 Break out AXI4 memory to a separate module 
This commit also adds support for setting the AXI_TEST and VERBOSE
defines as plusargs or parameters
 2016-02-18 21:26:18 +01:00
Clifford Wolf c4c477180e Merged various testbench changes from compressed ISA branch 2016-02-03 16:33:01 +01:00
Clifford Wolf 8d9f048785 Using riscv32-unknown-elf- toolchain 2015-11-03 18:59:12 +01:00
Clifford Wolf 8eaeebf486 Progress in "make check" 2015-10-15 15:45:19 +02:00
Clifford Wolf 07f28068f6 Added "make check" 2015-10-14 23:26:04 +02:00
Clifford Wolf d8c3157bf8 Improved firmware for vivado "system" example 2015-07-16 11:11:45 +02:00
Clifford Wolf 4601fa23e9 Added -Werror 2015-07-04 16:31:26 +02:00
Clifford Wolf 91f75bdf1f Turned gcc warnings up to eleven 
Patch by Larry Doolittle
 2015-07-04 11:47:19 +02:00
Clifford Wolf 2df7aadc7a Fixed typo in Makefile 2015-07-03 18:43:37 +02:00
Clifford Wolf 476046c177 Minor Makefile changes 2015-07-02 11:01:21 +02:00
Clifford Wolf a7f9b7fbf3 Some testbench-related improvements 
Patch by Larry Doolittle
 2015-07-02 10:45:35 +02:00
Clifford Wolf 9d809eb0d9 Added TOC to README 2015-06-30 12:25:05 +02:00
Clifford Wolf 997c5ce341 Added "make test_synth" 2015-06-30 01:46:25 +02:00
Clifford Wolf 818faffe25 Improved IRQ documentation, added assembler macros 2015-06-28 02:10:45 +02:00
Clifford Wolf 7b17773bfc Added mul tests from riscv-tests 2015-06-27 22:18:24 +02:00
Clifford Wolf 44571601c1 Added "make test_sp" 2015-06-26 23:54:12 +02:00
Clifford Wolf 0be990bd04 Added Pico Co-Processor Interface (PCPI) 2015-06-26 23:15:35 +02:00
Clifford Wolf d4331491a8 Test firmware refactoring 2015-06-26 23:15:30 +02:00
Clifford Wolf 23b700cf73 Added basic IRQ support 2015-06-25 14:08:39 +02:00
Clifford Wolf 9df9d7ff90 Improved Xilinx example 2015-06-06 20:14:58 +02:00
Clifford Wolf c55d537401 Improved AXI tests 2015-06-06 19:22:28 +02:00
Clifford Wolf 77ba5a1897 Initial import 2015-06-06 14:14:32 +02:00