Commit Graph

633 Commits

Author SHA1 Message Date
colin.liang f6b14b047b Refine memory interface. Change start addr from 10000 to 0. 2023-01-18 21:09:57 +08:00
colin.liang 780c18e008 Remove debug function. 2023-01-17 21:04:09 +08:00
colin.liang dfc2c47327 Refine memory interface. 2023-01-17 20:39:24 +08:00
colin.liang 7f42e7f7a4 Refine picorv code. 2023-01-17 14:51:40 +08:00
colin.liang b03844d9ac remove irq in testbench. 2023-01-17 13:01:41 +08:00
colin.liang dcab0c3178 Delete trace code in picorv. 2023-01-17 13:00:31 +08:00
colin.liang ef6fb8848f Remove irq support. 2023-01-16 20:41:28 +08:00
colin.liang 2b3f3d3f3d Move debug from core to test bench. 2023-01-13 16:11:36 +08:00
colin.liang 287e1416ea Add console.log output. 2023-01-13 15:46:50 +08:00
colin.liang e345620054 Add dhry.hex build in the top makefile. 2023-01-13 15:32:58 +08:00
colin.liang 2cf0e04e02 Add disasmmably. 2023-01-13 15:10:40 +08:00
colin.liang eab4b918b9 Refine testbench.v. 2023-01-13 14:59:49 +08:00
colin.liang e44af58d63 Refine hex file index from verialtor c code. 2023-01-13 14:49:21 +08:00
colin.liang ce40766cbd Refine tester. test common and dhry at the same time. 2023-01-12 21:18:03 +08:00
colin.liang 361dba595d remove compressed_instr. 2023-01-12 19:55:50 +08:00
colin.liang 6e318265dc format code. 2023-01-12 19:00:41 +08:00
colin.liang 2d6b66d3b4 remove BARREL_SHIFTER. 2023-01-12 17:48:48 +08:00
colin.liang 3cfab6b748 remove TWO_STAGE_SHIFT. 2023-01-12 17:36:57 +08:00
colin.liang b5edff85f7 Remove TWO_CYCLE_COMPARE. 2023-01-12 17:35:47 +08:00
colin.liang bb0bf253eb remove TWO_CYCLE_ALU. 2023-01-12 17:31:14 +08:00
colin.liang 4beed17d0a Format code. 2023-01-12 17:22:59 +08:00
colin.liang 665f26dc63 remove unsed. 2023-01-12 17:09:59 +08:00
colin.liang 1436980611 remove WITH_PCPI. 2023-01-12 17:07:04 +08:00
colin.liang 92b7265264 Remote unuse fast mul code. 2023-01-12 17:04:17 +08:00
colin.liang 9adf1c0029 Remove Config of IRQ, Use reg module from latch. 2023-01-12 17:02:34 +08:00
colin.liang 9c0d7d7593 Remove MUL DIV config paremeter. 2023-01-12 16:27:05 +08:00
colin.liang af85947a58 Remote ENABLE_REGS_DUALPORT and init reg zero. 2023-01-12 16:09:10 +08:00
colin.liang 8b3d3390f5 Remove CATCH_MISALIGN CATCH_ILLINSN. 2023-01-12 16:05:34 +08:00
colin.liang d9e14153fc Remote COMPOSE_ISA support. 2023-01-12 15:58:11 +08:00
colin.liang b99c193120 Remove counter parameter. Default enable. 2023-01-10 20:52:25 +08:00
colin.liang f714dd5da4 Change stackpoint to h0001_0000. 2023-01-10 20:28:17 +08:00
colin.liang a015d7d595 Remove no use default config. 2023-01-10 19:59:13 +08:00
colin.liang d1b0213ff0 Default donot use compress isa. 2023-01-10 19:56:05 +08:00
colin.liang d4ce161c1c format testbench. 2023-01-10 15:44:16 +08:00
colin.liang 42e498aa28 mv from picorv to testbench 2023-01-10 15:43:08 +08:00
colin.liang 0e6103f51f Remove wb RAM. 2023-01-09 20:05:40 +08:00
colin.liang 6d34315889 remove unused picorv32. 2023-01-09 18:23:42 +08:00
colin.liang 3feacd84c4 Delete RISCV_FORMAL_ALTOPS. 2023-01-09 15:35:06 +08:00
colin.liang f02c0b23c4 Delete axi ez sp. 2023-01-09 15:33:37 +08:00
colin.liang c676992a07 Remove RISCV_FORMAL. 2023-01-09 13:26:32 +08:00
colin.liang 3bda5c9e63 Fix to run environment problem. 2023-01-07 19:37:25 +08:00
Claire Xen f00a88c36e
Merge pull request #209 from YosysHQ/micko/cleanups
Cleanups
2022-01-03 16:03:13 +01:00
Miodrag Milanovic e8dbd9ac6a Fix dhrystone 2021-12-27 11:09:39 +01:00
Miodrag Milanovic d330c1406b fix for check target 2021-12-27 10:52:12 +01:00
Miodrag Milanovic b08952b896 Fix gitignore 2021-12-27 10:18:51 +01:00
Miodrag Milanovic 0b87954437 Fix simulation 2021-12-27 10:18:30 +01:00
Claire Xen 1d9f5b7678
Merge pull request #166 from tommythorn/master
Enable the use of 64-bit riscv tools
2021-12-06 16:10:29 +01:00
Claire Xen 6b1397700f
Merge pull request #173 from tonymmm1/hx8kdemo-nextpnr
changed hx8kdemo from arachne-pnr to nextpnr-ice40
2021-12-06 16:09:28 +01:00
Claire Xen 354f65ab4a
Merge pull request #202 from osresearch/icebreaker-fast-mul
picosoc: enable fast multiply option for icebreaker
2021-12-06 16:09:00 +01:00
Miodrag Milanovic e8edf98772 add license file 2021-12-03 15:54:08 +01:00