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dec update

This commit is contained in:
​Laraib Khan 2020-11-24 15:49:49 +05:00
parent 5ed044d54b
commit 220b0575c1
97 changed files with 29758 additions and 28812 deletions
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2130
el2_dec.anno.json
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el2_dec.fir
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el2_dec.v
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el2_exu_alu_ctl.anno.json
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@ -1,16 +1,42 @@
[ [
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_way", "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_hist",
"sources":[ "sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_way" "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_hist",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_prett", "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pred_correct_out",
"sources":[ "sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett" "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
] ]
}, },
{ {
@ -22,21 +48,38 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_br_start_error", "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_final_out",
"sources":[ "sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_br_start_error" "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_ataken", "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_ataken",
"sources":[ "sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
@ -47,30 +90,9 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pret", "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_toffset",
"sources":[ "sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret" "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_toffset"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pc4",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pc4"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_toffset",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_toffset"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_br_error",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_br_error"
] ]
}, },
{ {
@ -81,72 +103,15 @@
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_boffset",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_boffset"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_hist",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_hist",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pcall",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_final_out",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
@ -158,10 +123,10 @@
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_path_out", "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_path_out",
"sources":[ "sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pc_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pc_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_brimm_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_brimm_in",
@ -171,19 +136,40 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_misp", "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pret",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pja",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pc4",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pc4"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_misp",
"sources":[ "sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
@ -194,30 +180,44 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pred_correct_out", "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_way",
"sources":[ "sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_way"
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pja", "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pcall",
"sources":[ "sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja" "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_br_start_error",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_br_start_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_br_error",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_br_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_prett",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_boffset",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_boffset"
] ]
}, },
{ {

326
el2_exu_alu_ctl.fir
View File

@ -51,7 +51,7 @@ circuit el2_exu_alu_ctl :
module el2_exu_alu_ctl : module el2_exu_alu_ctl :
input clock : Clock input clock : Clock
input reset : AsyncReset input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}}
node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60] node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
@ -102,9 +102,9 @@ circuit el2_exu_alu_ctl :
aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8] aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8]
node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18] node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18]
node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22] node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22]
node _T_26 = not(_T_25) @[el2_exu_alu_ctl.scala 45:14] node _T_26 = eq(_T_25, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:14]
node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32] node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32]
node _T_28 = not(_T_27) @[el2_exu_alu_ctl.scala 45:29] node _T_28 = eq(_T_27, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:29]
node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27] node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27]
node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44] node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44]
node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37] node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37]
@ -112,20 +112,20 @@ circuit el2_exu_alu_ctl :
node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71] node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71]
node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66] node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66]
node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83] node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83]
node _T_36 = not(_T_35) @[el2_exu_alu_ctl.scala 45:78] node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:78]
node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76] node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76]
node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50] node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50]
node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50] node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50]
node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38] node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38]
node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29] node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29]
node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34] node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34]
node _T_39 = not(io.ap.unsign) @[el2_exu_alu_ctl.scala 50:30] node _T_39 = eq(io.ap.unsign, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 50:30]
node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51] node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51]
node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44] node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44]
node _T_42 = not(cout) @[el2_exu_alu_ctl.scala 50:78] node _T_42 = eq(cout, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 50:78]
node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76] node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76]
node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58] node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58]
node ge = not(lt) @[el2_exu_alu_ctl.scala 51:29] node ge = eq(lt, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 51:29]
node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19] node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19]
node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50] node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50]
node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16] node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16]
@ -190,12 +190,12 @@ circuit el2_exu_alu_ctl :
shift_amount <= _T_97 @[Mux.scala 27:72] shift_amount <= _T_97 @[Mux.scala 27:72]
wire shift_mask : UInt<32> wire shift_mask : UInt<32>
shift_mask <= UInt<1>("h00") shift_mask <= UInt<1>("h00")
wire _T_98 : UInt<1>[5] @[el2_lib.scala 161:48] wire _T_98 : UInt<1>[5] @[el2_lib.scala 162:48]
_T_98[0] <= io.ap.sll @[el2_lib.scala 161:48] _T_98[0] <= io.ap.sll @[el2_lib.scala 162:48]
_T_98[1] <= io.ap.sll @[el2_lib.scala 161:48] _T_98[1] <= io.ap.sll @[el2_lib.scala 162:48]
_T_98[2] <= io.ap.sll @[el2_lib.scala 161:48] _T_98[2] <= io.ap.sll @[el2_lib.scala 162:48]
_T_98[3] <= io.ap.sll @[el2_lib.scala 161:48] _T_98[3] <= io.ap.sll @[el2_lib.scala 162:48]
_T_98[4] <= io.ap.sll @[el2_lib.scala 161:48] _T_98[4] <= io.ap.sll @[el2_lib.scala 162:48]
node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58] node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58]
node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58] node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58]
node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58] node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58]
@ -206,38 +206,38 @@ circuit el2_exu_alu_ctl :
shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14] shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14]
wire shift_extend : UInt<63> wire shift_extend : UInt<63>
shift_extend <= UInt<1>("h00") shift_extend <= UInt<1>("h00")
wire _T_106 : UInt<1>[31] @[el2_lib.scala 161:48] wire _T_106 : UInt<1>[31] @[el2_lib.scala 162:48]
_T_106[0] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[0] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[1] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[1] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[2] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[2] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[3] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[3] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[4] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[4] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[5] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[5] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[6] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[6] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[7] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[7] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[8] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[8] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[9] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[9] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[10] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[10] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[11] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[11] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[12] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[12] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[13] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[13] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[14] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[14] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[15] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[15] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[16] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[16] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[17] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[17] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[18] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[18] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[19] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[19] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[20] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[20] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[21] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[21] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[22] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[22] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[23] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[23] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[24] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[24] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[25] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[25] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[26] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[26] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[27] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[27] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[28] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[28] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[29] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[29] <= io.ap.sra @[el2_lib.scala 162:48]
_T_106[30] <= io.ap.sra @[el2_lib.scala 161:48] _T_106[30] <= io.ap.sra @[el2_lib.scala 162:48]
node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58] node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58]
node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58] node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58]
node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58] node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58]
@ -269,38 +269,38 @@ circuit el2_exu_alu_ctl :
node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58] node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58]
node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58] node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58]
node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61] node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61]
wire _T_138 : UInt<1>[31] @[el2_lib.scala 161:48] wire _T_138 : UInt<1>[31] @[el2_lib.scala 162:48]
_T_138[0] <= _T_137 @[el2_lib.scala 161:48] _T_138[0] <= _T_137 @[el2_lib.scala 162:48]
_T_138[1] <= _T_137 @[el2_lib.scala 161:48] _T_138[1] <= _T_137 @[el2_lib.scala 162:48]
_T_138[2] <= _T_137 @[el2_lib.scala 161:48] _T_138[2] <= _T_137 @[el2_lib.scala 162:48]
_T_138[3] <= _T_137 @[el2_lib.scala 161:48] _T_138[3] <= _T_137 @[el2_lib.scala 162:48]
_T_138[4] <= _T_137 @[el2_lib.scala 161:48] _T_138[4] <= _T_137 @[el2_lib.scala 162:48]
_T_138[5] <= _T_137 @[el2_lib.scala 161:48] _T_138[5] <= _T_137 @[el2_lib.scala 162:48]
_T_138[6] <= _T_137 @[el2_lib.scala 161:48] _T_138[6] <= _T_137 @[el2_lib.scala 162:48]
_T_138[7] <= _T_137 @[el2_lib.scala 161:48] _T_138[7] <= _T_137 @[el2_lib.scala 162:48]
_T_138[8] <= _T_137 @[el2_lib.scala 161:48] _T_138[8] <= _T_137 @[el2_lib.scala 162:48]
_T_138[9] <= _T_137 @[el2_lib.scala 161:48] _T_138[9] <= _T_137 @[el2_lib.scala 162:48]
_T_138[10] <= _T_137 @[el2_lib.scala 161:48] _T_138[10] <= _T_137 @[el2_lib.scala 162:48]
_T_138[11] <= _T_137 @[el2_lib.scala 161:48] _T_138[11] <= _T_137 @[el2_lib.scala 162:48]
_T_138[12] <= _T_137 @[el2_lib.scala 161:48] _T_138[12] <= _T_137 @[el2_lib.scala 162:48]
_T_138[13] <= _T_137 @[el2_lib.scala 161:48] _T_138[13] <= _T_137 @[el2_lib.scala 162:48]
_T_138[14] <= _T_137 @[el2_lib.scala 161:48] _T_138[14] <= _T_137 @[el2_lib.scala 162:48]
_T_138[15] <= _T_137 @[el2_lib.scala 161:48] _T_138[15] <= _T_137 @[el2_lib.scala 162:48]
_T_138[16] <= _T_137 @[el2_lib.scala 161:48] _T_138[16] <= _T_137 @[el2_lib.scala 162:48]
_T_138[17] <= _T_137 @[el2_lib.scala 161:48] _T_138[17] <= _T_137 @[el2_lib.scala 162:48]
_T_138[18] <= _T_137 @[el2_lib.scala 161:48] _T_138[18] <= _T_137 @[el2_lib.scala 162:48]
_T_138[19] <= _T_137 @[el2_lib.scala 161:48] _T_138[19] <= _T_137 @[el2_lib.scala 162:48]
_T_138[20] <= _T_137 @[el2_lib.scala 161:48] _T_138[20] <= _T_137 @[el2_lib.scala 162:48]
_T_138[21] <= _T_137 @[el2_lib.scala 161:48] _T_138[21] <= _T_137 @[el2_lib.scala 162:48]
_T_138[22] <= _T_137 @[el2_lib.scala 161:48] _T_138[22] <= _T_137 @[el2_lib.scala 162:48]
_T_138[23] <= _T_137 @[el2_lib.scala 161:48] _T_138[23] <= _T_137 @[el2_lib.scala 162:48]
_T_138[24] <= _T_137 @[el2_lib.scala 161:48] _T_138[24] <= _T_137 @[el2_lib.scala 162:48]
_T_138[25] <= _T_137 @[el2_lib.scala 161:48] _T_138[25] <= _T_137 @[el2_lib.scala 162:48]
_T_138[26] <= _T_137 @[el2_lib.scala 161:48] _T_138[26] <= _T_137 @[el2_lib.scala 162:48]
_T_138[27] <= _T_137 @[el2_lib.scala 161:48] _T_138[27] <= _T_137 @[el2_lib.scala 162:48]
_T_138[28] <= _T_137 @[el2_lib.scala 161:48] _T_138[28] <= _T_137 @[el2_lib.scala 162:48]
_T_138[29] <= _T_137 @[el2_lib.scala 161:48] _T_138[29] <= _T_137 @[el2_lib.scala 162:48]
_T_138[30] <= _T_137 @[el2_lib.scala 161:48] _T_138[30] <= _T_137 @[el2_lib.scala 162:48]
node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58] node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58]
node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58] node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58]
node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58] node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58]
@ -332,38 +332,38 @@ circuit el2_exu_alu_ctl :
node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58] node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58]
node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58] node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58]
node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44] node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44]
wire _T_170 : UInt<1>[31] @[el2_lib.scala 161:48] wire _T_170 : UInt<1>[31] @[el2_lib.scala 162:48]
_T_170[0] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[0] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[1] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[1] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[2] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[2] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[3] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[3] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[4] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[4] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[5] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[5] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[6] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[6] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[7] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[7] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[8] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[8] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[9] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[9] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[10] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[10] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[11] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[11] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[12] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[12] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[13] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[13] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[14] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[14] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[15] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[15] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[16] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[16] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[17] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[17] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[18] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[18] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[19] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[19] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[20] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[20] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[21] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[21] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[22] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[22] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[23] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[23] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[24] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[24] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[25] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[25] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[26] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[26] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[27] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[27] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[28] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[28] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[29] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[29] <= io.ap.sll @[el2_lib.scala 162:48]
_T_170[30] <= io.ap.sll @[el2_lib.scala 161:48] _T_170[30] <= io.ap.sll @[el2_lib.scala 162:48]
node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58] node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58]
node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58] node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58]
node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58] node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58]
@ -411,11 +411,11 @@ circuit el2_exu_alu_ctl :
node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41] node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41]
node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53] node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53]
node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41] node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41]
node _T_212 = not(io.ap.slt) @[el2_exu_alu_ctl.scala 78:56] node _T_212 = eq(io.ap.slt, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 78:56]
node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54] node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54]
node _T_213 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 79:41] node _T_213 = or(io.ap.jal, io.pp_in.bits.pcall) @[el2_exu_alu_ctl.scala 79:41]
node _T_214 = or(_T_213, io.pp_in.pja) @[el2_exu_alu_ctl.scala 79:58] node _T_214 = or(_T_213, io.pp_in.bits.pja) @[el2_exu_alu_ctl.scala 79:63]
node sel_pc = or(_T_214, io.pp_in.pret) @[el2_exu_alu_ctl.scala 79:73] node sel_pc = or(_T_214, io.pp_in.bits.pret) @[el2_exu_alu_ctl.scala 79:83]
node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47] node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47]
node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63] node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63]
node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32] node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32]
@ -437,14 +437,14 @@ circuit el2_exu_alu_ctl :
node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 212:26] node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 212:26]
node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 212:64] node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 212:64]
node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 212:76] node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 212:76]
node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:8] node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:20]
node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:27] node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:39]
node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:14] node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:26]
node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:52] node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:64]
node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:27] node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:39]
node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:16] node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:28]
node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:14] node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:26]
node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:52] node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:64]
node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72] node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72] node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72] node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72]
@ -452,7 +452,7 @@ circuit el2_exu_alu_ctl :
node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72] node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72]
wire _T_247 : UInt<19> @[Mux.scala 27:72] wire _T_247 : UInt<19> @[Mux.scala 27:72]
_T_247 <= _T_246 @[Mux.scala 27:72] _T_247 <= _T_246 @[Mux.scala 27:72]
node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:82] node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:94]
node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58] node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24] node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24]
@ -476,9 +476,9 @@ circuit el2_exu_alu_ctl :
_T_267 <= _T_266 @[Mux.scala 27:72] _T_267 <= _T_266 @[Mux.scala 27:72]
node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56] node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56]
result <= _T_268 @[el2_exu_alu_ctl.scala 88:16] result <= _T_268 @[el2_exu_alu_ctl.scala 88:16]
node _T_269 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 96:45] node _T_269 = or(io.ap.jal, io.pp_in.bits.pcall) @[el2_exu_alu_ctl.scala 96:45]
node _T_270 = or(_T_269, io.pp_in.pja) @[el2_exu_alu_ctl.scala 97:20] node _T_270 = or(_T_269, io.pp_in.bits.pja) @[el2_exu_alu_ctl.scala 97:25]
node any_jal = or(_T_270, io.pp_in.pret) @[el2_exu_alu_ctl.scala 98:20] node any_jal = or(_T_270, io.pp_in.bits.pret) @[el2_exu_alu_ctl.scala 98:25]
node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40] node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40]
node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59] node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59]
node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46] node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46]
@ -507,9 +507,9 @@ circuit el2_exu_alu_ctl :
node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45] node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45]
node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82] node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82]
node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62] node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62]
node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:70] node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:80]
node _T_296 = neq(io.pp_in.prett, _T_295) @[el2_exu_alu_ctl.scala 114:62] node _T_296 = neq(io.pp_in.bits.prett, _T_295) @[el2_exu_alu_ctl.scala 114:72]
node target_mispredict = and(io.pp_in.pret, _T_296) @[el2_exu_alu_ctl.scala 114:44] node target_mispredict = and(io.pp_in.bits.pret, _T_296) @[el2_exu_alu_ctl.scala 114:49]
node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42] node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42]
node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60] node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60]
node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81] node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81]
@ -527,42 +527,42 @@ circuit el2_exu_alu_ctl :
io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26] io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26]
wire newhist : UInt<2> wire newhist : UInt<2>
newhist <= UInt<1>("h00") newhist <= UInt<1>("h00")
node _T_310 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:35] node _T_310 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:40]
node _T_311 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:55] node _T_311 = bits(io.pp_in.bits.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:65]
node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:39] node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:44]
node _T_313 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:77] node _T_313 = bits(io.pp_in.bits.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:92]
node _T_314 = not(_T_313) @[el2_exu_alu_ctl.scala 122:63] node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 122:73]
node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:81] node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:96]
node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:60] node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:70]
node _T_317 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:20] node _T_317 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:25]
node _T_318 = not(_T_317) @[el2_exu_alu_ctl.scala 123:6] node _T_318 = eq(_T_317, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 123:6]
node _T_319 = not(actual_taken) @[el2_exu_alu_ctl.scala 123:26] node _T_319 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 123:31]
node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:24] node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:29]
node _T_321 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:58] node _T_321 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:68]
node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:62] node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:72]
node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:42] node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:47]
node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58] node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58]
newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14] newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14]
io.predict_p_out.way <= io.pp_in.way @[el2_exu_alu_ctl.scala 125:30] io.predict_p_out.bits.way <= io.pp_in.bits.way @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.pja <= io.pp_in.pja @[el2_exu_alu_ctl.scala 125:30] io.predict_p_out.bits.pja <= io.pp_in.bits.pja @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.pret <= io.pp_in.pret @[el2_exu_alu_ctl.scala 125:30] io.predict_p_out.bits.pret <= io.pp_in.bits.pret @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.pcall <= io.pp_in.pcall @[el2_exu_alu_ctl.scala 125:30] io.predict_p_out.bits.pcall <= io.pp_in.bits.pcall @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.prett <= io.pp_in.prett @[el2_exu_alu_ctl.scala 125:30] io.predict_p_out.bits.prett <= io.pp_in.bits.prett @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.br_start_error <= io.pp_in.br_start_error @[el2_exu_alu_ctl.scala 125:30] io.predict_p_out.bits.br_start_error <= io.pp_in.bits.br_start_error @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.br_error <= io.pp_in.br_error @[el2_exu_alu_ctl.scala 125:30] io.predict_p_out.bits.br_error <= io.pp_in.bits.br_error @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.toffset <= io.pp_in.bits.toffset @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.hist <= io.pp_in.bits.hist @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.pc4 <= io.pp_in.bits.pc4 @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.boffset <= io.pp_in.bits.boffset @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.ataken <= io.pp_in.bits.ataken @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.bits.misp <= io.pp_in.bits.misp @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30] io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30]
io.predict_p_out.toffset <= io.pp_in.toffset @[el2_exu_alu_ctl.scala 125:30] node _T_325 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 126:38]
io.predict_p_out.hist <= io.pp_in.hist @[el2_exu_alu_ctl.scala 125:30] node _T_326 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 126:58]
io.predict_p_out.pc4 <= io.pp_in.pc4 @[el2_exu_alu_ctl.scala 125:30] node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:56]
io.predict_p_out.boffset <= io.pp_in.boffset @[el2_exu_alu_ctl.scala 125:30] node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:95]
io.predict_p_out.ataken <= io.pp_in.ataken @[el2_exu_alu_ctl.scala 125:30] node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:76]
io.predict_p_out.misp <= io.pp_in.misp @[el2_exu_alu_ctl.scala 125:30] io.predict_p_out.bits.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:35]
node _T_325 = not(io.flush_upper_x) @[el2_exu_alu_ctl.scala 126:33] io.predict_p_out.bits.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:35]
node _T_326 = not(io.flush_lower_r) @[el2_exu_alu_ctl.scala 126:53] io.predict_p_out.bits.hist <= newhist @[el2_exu_alu_ctl.scala 128:35]
node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:51]
node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:90]
node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:71]
io.predict_p_out.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:30]
io.predict_p_out.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:30]
io.predict_p_out.hist <= newhist @[el2_exu_alu_ctl.scala 128:30]

114
el2_exu_alu_ctl.v
View File

@ -50,20 +50,20 @@ module el2_exu_alu_ctl(
input [31:0] io_a_in, input [31:0] io_a_in,
input [31:0] io_b_in, input [31:0] io_b_in,
input [30:0] io_pc_in, input [30:0] io_pc_in,
input io_pp_in_misp,
input io_pp_in_ataken,
input io_pp_in_boffset,
input io_pp_in_pc4,
input [1:0] io_pp_in_hist,
input [11:0] io_pp_in_toffset,
input io_pp_in_valid, input io_pp_in_valid,
input io_pp_in_br_error, input io_pp_in_bits_misp,
input io_pp_in_br_start_error, input io_pp_in_bits_ataken,
input [30:0] io_pp_in_prett, input io_pp_in_bits_boffset,
input io_pp_in_pcall, input io_pp_in_bits_pc4,
input io_pp_in_pret, input [1:0] io_pp_in_bits_hist,
input io_pp_in_pja, input [11:0] io_pp_in_bits_toffset,
input io_pp_in_way, input io_pp_in_bits_br_error,
input io_pp_in_bits_br_start_error,
input [30:0] io_pp_in_bits_prett,
input io_pp_in_bits_pcall,
input io_pp_in_bits_pret,
input io_pp_in_bits_pja,
input io_pp_in_bits_way,
input [11:0] io_brimm_in, input [11:0] io_brimm_in,
output [31:0] io_result_ff, output [31:0] io_result_ff,
output io_flush_upper_out, output io_flush_upper_out,
@ -71,20 +71,20 @@ module el2_exu_alu_ctl(
output [30:0] io_flush_path_out, output [30:0] io_flush_path_out,
output [30:0] io_pc_ff, output [30:0] io_pc_ff,
output io_pred_correct_out, output io_pred_correct_out,
output io_predict_p_out_misp,
output io_predict_p_out_ataken,
output io_predict_p_out_boffset,
output io_predict_p_out_pc4,
output [1:0] io_predict_p_out_hist,
output [11:0] io_predict_p_out_toffset,
output io_predict_p_out_valid, output io_predict_p_out_valid,
output io_predict_p_out_br_error, output io_predict_p_out_bits_misp,
output io_predict_p_out_br_start_error, output io_predict_p_out_bits_ataken,
output [30:0] io_predict_p_out_prett, output io_predict_p_out_bits_boffset,
output io_predict_p_out_pcall, output io_predict_p_out_bits_pc4,
output io_predict_p_out_pret, output [1:0] io_predict_p_out_bits_hist,
output io_predict_p_out_pja, output [11:0] io_predict_p_out_bits_toffset,
output io_predict_p_out_way output io_predict_p_out_bits_br_error,
output io_predict_p_out_bits_br_start_error,
output [30:0] io_predict_p_out_bits_prett,
output io_predict_p_out_bits_pcall,
output io_predict_p_out_bits_pret,
output io_predict_p_out_bits_pja,
output io_predict_p_out_bits_way
); );
`ifdef RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0; reg [31:0] _RAND_0;
@ -172,9 +172,9 @@ module el2_exu_alu_ctl(
wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41] wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41]
wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56] wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56]
wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54] wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54]
wire _T_213 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 79:41] wire _T_213 = io_ap_jal | io_pp_in_bits_pcall; // @[el2_exu_alu_ctl.scala 79:41]
wire _T_214 = _T_213 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 79:58] wire _T_214 = _T_213 | io_pp_in_bits_pja; // @[el2_exu_alu_ctl.scala 79:63]
wire sel_pc = _T_214 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 79:73] wire sel_pc = _T_214 | io_pp_in_bits_pret; // @[el2_exu_alu_ctl.scala 79:83]
wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40] wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40]
wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58]
@ -183,9 +183,9 @@ module el2_exu_alu_ctl(
wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27] wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27]
wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28] wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28]
wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26] wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26]
wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:8] wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:20]
wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:14] wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:26]
wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:14] wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:26]
wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72]
@ -222,24 +222,24 @@ module el2_exu_alu_ctl(
wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45] wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45]
wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82] wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82]
wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62] wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62]
wire _T_296 = io_pp_in_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:62] wire _T_296 = io_pp_in_bits_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:72]
wire target_mispredict = io_pp_in_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:44] wire target_mispredict = io_pp_in_bits_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:49]
wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42] wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42]
wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60] wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60]
wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81] wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81]
wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97] wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97]
wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95] wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95]
wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119] wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119]
wire _T_312 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:39] wire _T_312 = io_pp_in_bits_hist[1] & io_pp_in_bits_hist[0]; // @[el2_exu_alu_ctl.scala 122:44]
wire _T_314 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:63] wire _T_314 = ~io_pp_in_bits_hist[0]; // @[el2_exu_alu_ctl.scala 122:73]
wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:81] wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:96]
wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:60] wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:70]
wire _T_318 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 123:6] wire _T_318 = ~io_pp_in_bits_hist[1]; // @[el2_exu_alu_ctl.scala 123:6]
wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:24] wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:29]
wire _T_322 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:62] wire _T_322 = io_pp_in_bits_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:72]
wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:42] wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:47]
wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:51] wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:56]
wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:90] wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:95]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_io_l1clk), .io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
@ -258,20 +258,20 @@ module el2_exu_alu_ctl(
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22] assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22]
assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12] assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12]
assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26] assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26]
assign io_predict_p_out_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:30]
assign io_predict_p_out_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:30]
assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:30]
assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:35]
assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:35]
assign io_predict_p_out_prett = io_pp_in_prett; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:35]
assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_br_error = io_pp_in_bits_br_error; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_br_start_error = io_pp_in_bits_br_start_error; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_prett = io_pp_in_bits_prett; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_pcall = io_pp_in_bits_pcall; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[el2_exu_alu_ctl.scala 125:30]
assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[el2_exu_alu_ctl.scala 125:30]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 511:17] assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 511:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]

28
el2_exu_mul_ctl.fir
View File

@ -99,7 +99,7 @@ circuit el2_exu_mul_ctl :
node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58] node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58]
node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:71] node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:71]
rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14] rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14]
node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 36:52] node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 29:52]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
rvclkhdr.clock <= clock rvclkhdr.clock <= clock
rvclkhdr.reset <= reset rvclkhdr.reset <= reset
@ -108,8 +108,8 @@ circuit el2_exu_mul_ctl :
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_9 <= io.mul_p.bits.low @[el2_lib.scala 514:16] _T_9 <= io.mul_p.bits.low @[el2_lib.scala 514:16]
low_x <= _T_9 @[el2_exu_mul_ctl.scala 36:9] low_x <= _T_9 @[el2_exu_mul_ctl.scala 29:9]
node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 37:44] node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 30:44]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 528:23] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 528:23]
rvclkhdr_1.clock <= clock rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset rvclkhdr_1.reset <= reset
@ -118,8 +118,8 @@ circuit el2_exu_mul_ctl :
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24]
reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16] reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16]
_T_11 <= rs1_ext_in @[el2_lib.scala 534:16] _T_11 <= rs1_ext_in @[el2_lib.scala 534:16]
rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 37:9] rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 30:9]
node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 38:45] node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 31:45]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 528:23] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 528:23]
rvclkhdr_2.clock <= clock rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset rvclkhdr_2.reset <= reset
@ -128,18 +128,18 @@ circuit el2_exu_mul_ctl :
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24] rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24]
reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16] reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16]
_T_13 <= rs2_ext_in @[el2_lib.scala 534:16] _T_13 <= rs2_ext_in @[el2_lib.scala 534:16]
rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 38:9] rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 31:9]
node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 40:20] node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 33:20]
prod_x <= _T_14 @[el2_exu_mul_ctl.scala 40:10] prod_x <= _T_14 @[el2_exu_mul_ctl.scala 33:10]
node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:36] node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 34:36]
node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 41:29] node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 34:29]
node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 41:52] node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 34:52]
node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:67] node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 34:67]
node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 41:83] node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 34:83]
node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72] node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72] node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72] node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72]
wire _T_23 : UInt<32> @[Mux.scala 27:72] wire _T_23 : UInt<32> @[Mux.scala 27:72]
_T_23 <= _T_22 @[Mux.scala 27:72] _T_23 <= _T_22 @[Mux.scala 27:72]
io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 41:15] io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 34:15]

6
el2_exu_mul_ctl.v
View File

@ -68,8 +68,8 @@ module el2_exu_mul_ctl(
reg low_x; // @[el2_lib.scala 514:16] reg low_x; // @[el2_lib.scala 514:16]
reg [32:0] rs1_x; // @[el2_lib.scala 534:16] reg [32:0] rs1_x; // @[el2_lib.scala 534:16]
reg [32:0] rs2_x; // @[el2_lib.scala 534:16] reg [32:0] rs2_x; // @[el2_lib.scala 534:16]
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 40:20] wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 33:20]
wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 41:29] wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 34:29]
wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
@ -90,7 +90,7 @@ module el2_exu_mul_ctl(
.io_en(rvclkhdr_2_io_en), .io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode) .io_scan_mode(rvclkhdr_2_io_scan_mode)
); );
assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 41:15] assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 34:15]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 511:17] assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 511:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]

362
el2_ifu.anno.json
View File

@ -1,88 +1,28 @@
[ [
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error", "sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r" "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_rd_en", "sink":"~el2_ifu|el2_ifu>io_iccm_wren",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_dec_tlu_force_halt",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_rden",
"sources":[
"~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_dma_mem_write", "~el2_ifu|el2_ifu>io_dma_mem_write",
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_premux_data",
"sources":[
"~el2_ifu|el2_ifu>io_iccm_rd_data",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_ready",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_exu_flush_final",
@ -92,8 +32,8 @@
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
@ -122,58 +62,6 @@
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_rd_valid" "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_rd_valid"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start",
"sources":[
"~el2_ifu|el2_ifu>io_ic_eccerr",
"~el2_ifu|el2_ifu>io_ic_tag_perr",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data",
"sources":[
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_wr_data", "sink":"~el2_ifu|el2_ifu>io_iccm_wr_data",
@ -189,8 +77,8 @@
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
@ -215,50 +103,61 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr", "sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_dma_mem_addr", "~el2_ifu|el2_ifu>io_ic_eccerr",
"~el2_ifu|el2_ifu>io_dma_iccm_req", "~el2_ifu|el2_ifu>io_ic_tag_perr",
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", "~el2_ifu|el2_ifu>io_ifu_axi_rid",
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_wren", "sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_dma_mem_write",
"~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_rden",
"sources":[
"~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_dma_mem_write",
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data" "~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
] ]
}, },
{ {
@ -268,6 +167,62 @@
"~el2_ifu|el2_ifu>io_dec_i0_decode_d" "~el2_ifu|el2_ifu>io_dec_i0_decode_d"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_premux_data",
"sources":[
"~el2_ifu|el2_ifu>io_iccm_rd_data",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_rw_addr",
"sources":[
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_iccm_rd_ecc_single_err", "sink":"~el2_ifu|el2_ifu>io_ifu_iccm_rd_ecc_single_err",
@ -279,33 +234,8 @@
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall",
"sources":[
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r" "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
] ]
}, },
@ -318,17 +248,48 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_rw_addr", "sink":"~el2_ifu|el2_ifu>io_ic_rd_en",
"sources":[ "sources":[
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_dec_tlu_force_halt",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr",
"sources":[
"~el2_ifu|el2_ifu>io_dma_mem_addr",
"~el2_ifu|el2_ifu>io_dma_iccm_req",
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable" "~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data"
] ]
}, },
{ {
@ -338,6 +299,45 @@
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wrdata" "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wrdata"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_iccm_ready",
"sources":[
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
"~el2_ifu|el2_ifu>io_ic_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data",
"sources":[
"~el2_ifu|el2_ifu>io_exu_flush_final",
"~el2_ifu|el2_ifu>io_ic_rd_hit",
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
]
},
{ {
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"

1152
el2_ifu.fir
View File

File diff suppressed because it is too large Load Diff

1204
el2_ifu.v
View File

File diff suppressed because it is too large Load Diff

62
el2_lsu.anno.json
View File

@ -132,37 +132,6 @@
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m",
"sources":[
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_ready", "sink":"~el2_lsu|el2_lsu>io_dccm_ready",
@ -374,6 +343,37 @@
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r" "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m",
"sources":[
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_pkt",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_pkt",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_pkt",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_pkt",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned", "sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned",

2016
el2_lsu.fir
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1075
el2_lsu.v
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13482
el2_swerv.fir
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10900
el2_swerv.v
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8786
el2_swerv_wrapper.fir
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4897
el2_swerv_wrapper.v
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4
firrtl_black_box_resource_files.f
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@ -1 +1,3 @@
/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v /home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v
/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv

8
src/main/scala/dec/el2_dec.scala
View File

@ -96,7 +96,7 @@ class el2_dec_IO extends Bundle with el2_lib {
val lsu_idle_any = Input(Bool()) // lsu idle for halting val lsu_idle_any = Input(Bool()) // lsu idle for halting
val i0_brp = Flipped(Valid(new el2_br_pkt_t)) // branch packet val i0_brp = Input(new el2_br_pkt_t) // branch packet
val ifu_i0_bp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // BP index val ifu_i0_bp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // BP index
val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
@ -223,7 +223,7 @@ class el2_dec_IO extends Bundle with el2_lib {
val pred_correct_npc_x = Output(UInt(31.W)) // npc if prediction is correct at e2 stage val pred_correct_npc_x = Output(UInt(31.W)) // npc if prediction is correct at e2 stage
val dec_tlu_br0_r_pkt = Valid(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
@ -599,6 +599,6 @@ class el2_dec extends Module with param with RequireAsyncReset{
// debug command read data // debug command read data
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
} }
object decode extends App { object dec_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec())) println((new chisel3.stage.ChiselStage).emitVerilog( new el2_dec()))
} }

260
src/main/scala/dec/el2_dec_dec_ctl.scala
View File

@ -1,173 +1,125 @@
package dec package dec
import chisel3._ import chisel3._
import chisel3.util._ import include._
import lib._
class el2_dec_pkt_t extends Bundle{ class el2_dec_dec_ctl extends Module with el2_lib{
val alu = Bool()
val rs1 = Bool()
val rs2 = Bool()
val imm12 = Bool()
val rd = Bool()
val shimm5 = Bool()
val imm20 = Bool()
val pc = Bool()
val load = Bool()
val store = Bool()
val lsu = Bool()
val add = Bool()
val sub = Bool()
val land = Bool()
val lor = Bool()
val lxor = Bool()
val sll = Bool()
val sra = Bool()
val srl = Bool()
val slt = Bool()
val unsign = Bool()
val condbr = Bool()
val beq = Bool()
val bne = Bool()
val bge = Bool()
val blt = Bool()
val jal = Bool()
val by = Bool()
val half = Bool()
val word = Bool()
val csr_read = Bool()
val csr_clr = Bool()
val csr_set = Bool()
val csr_write = Bool()
val csr_imm = Bool()
val presync = Bool()
val postsync = Bool()
val ebreak = Bool()
val ecall = Bool()
val mret = Bool()
val mul = Bool()
val rs1_sign = Bool()
val rs2_sign = Bool()
val low = Bool()
val div = Bool()
val rem = Bool()
val fence = Bool()
val fence_i = Bool()
val pm_alu = Bool()
val legal = Bool()
}
class el2_dec_dec_ctl extends Module{
val io = IO (new Bundle{ val io = IO (new Bundle{
val ins = Input(UInt(32.W)) val ins = Input(UInt(32.W))
val out = Output(new el2_dec_pkt_t) val out = Output(new el2_dec_pkt_t)
}) })
def pattern(y : List[Int]) : Array[UInt] = { def pattern(y : List[Int]) : UInt = {
val pat : Array[UInt] = new Array[UInt](y.size) val pat : Array[UInt] = new Array[UInt](y.size)
for (i <- 0 until y.size){ for (i <- 0 until y.size){
pat(i) = if(y(i)>0) io.ins(y(i)) else !io.ins(y(i).abs) pat(i) = if(y(i)>=0) io.ins(y(i)) else !io.ins(y(i).abs)
} }
pat pat.reduce(_&_)
} }
io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4)) io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4))
io.out.rs1 := pattern(List(-14,-13,-2)).reduce(_&_) | pattern(List(-13,11,-2)).reduce(_&_) | io.out.rs1 := pattern(List(-14,-13,-2)) | pattern(List(-13,11,-2)) |
pattern(List(19,13,-2)).reduce(_&_) | pattern(List(-13,10,-2)).reduce(_&_) | pattern(List(19,13,-2)) | pattern(List(-13,10,-2)) |
pattern(List(-18,13,-2)).reduce(_&_) | pattern(List(-13,9,-2)).reduce(_&_) | pattern(List(18,13,-2)) | pattern(List(-13,9,-2)) |
pattern(List(17,13,-2)).reduce(_&_) | pattern(List(-13,8,-2)).reduce(_&_) | pattern(List(17,13,-2)) | pattern(List(-13,8,-2)) |
pattern(List(16,13,-2)).reduce(_&_) | pattern(List(-13,7,-2)).reduce(_&_) | pattern(List(16,13,-2)) | pattern(List(-13,7,-2)) |
pattern(List(15,13,-2)).reduce(_&_) |pattern(List(-4,-3)).reduce(_&_) | pattern(List(-6,-2)).reduce(_&_) pattern(List(15,13,-2)) |pattern(List(-4,-3)) | pattern(List(-6,-2))
io.out.rs2 := pattern(List(5,-4,-2)).reduce(_&_) | pattern(List(-6,5,-2)).reduce(_&_) io.out.rs2 := pattern(List(5,-4,-2)) | pattern(List(-6,5,-2))
io.out.imm12 := pattern(List(-4,-3,2)).reduce(_&_) | pattern(List(13,-5,4,-2)).reduce(_&_) | io.out.imm12 := pattern(List(-4,-3,2)) | pattern(List(13,-5,4,-2)) |
pattern(List(-13,-12,6,4)).reduce(_&_) | pattern(List(-12,-5,4,-2)).reduce(_&_) pattern(List(-13,-12,6,4)) | pattern(List(-12,-5,4,-2))
io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4) io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4)
io.out.shimm5 := pattern(List(-13,12,-5,4,-2)).reduce(_&_) io.out.shimm5 := pattern(List(-13,12,-5,4,-2))
io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2)) io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2))
io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3)) io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3))
io.out.load := pattern(List(-5,-4,-2)).reduce(_&_) io.out.load := pattern(List(-5,-4,-2))
io.out.store := pattern(List(-6,5,-4)).reduce(_&_) io.out.store := pattern(List(-6,5,-4))
io.out.lsu := pattern(List(-6,-4,-2)).reduce(_&_) io.out.lsu := pattern(List(-6,-4,-2))
io.out.add := pattern(List(-14,-13,-12,-5,4)).reduce(_&_) | pattern(List(-5,-3,2)).reduce(_&_) | io.out.add := pattern(List(-14,-13,-12,-5,4)) | pattern(List(-5,-3,2)) |
pattern(List(-30,-25,-14,-13,-12,-6,4,-2)).reduce(_&_) pattern(List(-30,-25,-14,-13,-12,-6,4,-2))
io.out.sub := pattern(List(30,-12,-6,5,4,-2)).reduce(_&_) | pattern(List(-25,-14,13,-6,4,-2)).reduce(_&_) | io.out.sub := pattern(List(30,-12,-6,5,4,-2)) | pattern(List(-25,-14,13,-6,4,-2)) |
pattern(List(-14,13,-5,4,-2)).reduce(_&_) | pattern(List(6,-4,-2)).reduce(_&_) pattern(List(-14,13,-5,4,-2)) | pattern(List(6,-4,-2))
io.out.land := pattern(List(14,13,12,-5,-2)).reduce(_&_) | pattern(List(-25,14,13,12,-6,-2)).reduce(_&_) io.out.land := pattern(List(14,13,12,-5,-2)) | pattern(List(-25,14,13,12,-6,-2))
io.out.lor := pattern(List(-6,3)).reduce(_&_) | pattern(List(-25,14,13,-12,-6,-2)).reduce(_&_) | io.out.lor := pattern(List(-6,3)) | pattern(List(-25,14,13,-12,-6,-2)) |
pattern(List(5,4,2)).reduce(_&_) | pattern(List(-13,-12,6,4)).reduce(_&_) | pattern(List(5,4,2)) | pattern(List(-13,-12,6,4)) |
pattern(List(14,13,-12,-5,-2)).reduce(_&_) pattern(List(14,13,-12,-5,-2))
io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)).reduce(_&_) | pattern(List(14,-13,-12,-5,4,-2)).reduce(_&_) io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)) | pattern(List(14,-13,-12,-5,4,-2))
io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2)).reduce(_&_) io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2))
io.out.sra := pattern(List(30,-13,12,-6,4,-2)).reduce(_&_) io.out.sra := pattern(List(30,-13,12,-6,4,-2))
io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2)).reduce(_&_) io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2))
io.out.slt := pattern(List(-25,-14,13,12,-6,4,-2)).reduce(_&_) | pattern(List(-14,13,-5,4,-2)).reduce(_&_) io.out.slt := pattern(List(-25,-14,13,-6,4,-2)) | pattern(List(-14,13,-5,4,-2))
io.out.unsign := pattern(List(-14,13,12,-5,-2)).reduce(_&_) | pattern(List(13,6,-4,-2)).reduce(_&_) | io.out.unsign := pattern(List(-14,13,12,-5,-2)) | pattern(List(13,6,-4,-2)) |
pattern(List(14,-5,-4)).reduce(_&_) | pattern(List(-25,-14,13,12,-6,-2)).reduce(_&_) | pattern(List(14,-5,-4)) | pattern(List(-25,-14,13,12,-6,-2)) |
pattern(List(25,14,12,-6,5,-2)).reduce(_&_) pattern(List(25,14,12,-6,5,-2))
io.out.condbr := pattern(List(6,-4,-2)).reduce(_&_) io.out.condbr := pattern(List(6,-4,-2))
io.out.beq := pattern(List(-14,-12,6,-4,-2)).reduce(_&_) io.out.beq := pattern(List(-14,-12,6,-4,-2))
io.out.bne := pattern(List(-14,12,6,-4,-2)).reduce(_&_) io.out.bne := pattern(List(-14,12,6,-4,-2))
io.out.bge := pattern(List(14,12,5,-4,-2)).reduce(_&_) io.out.bge := pattern(List(14,12,5,-4,-2))
io.out.blt := pattern(List(14,-12,5,-4,-2)).reduce(_&_) io.out.blt := pattern(List(14,-12,5,-4,-2))
io.out.jal := pattern(List(6,2)).reduce(_&_) io.out.jal := pattern(List(6,2))
io.out.by := pattern(List(-13,-12,-6,-4,-2)).reduce(_&_) io.out.by := pattern(List(-13,-12,-6,-4,-2))
io.out.half := pattern(List(12,-6,-4,-2)).reduce(_&_) io.out.half := pattern(List(12,-6,-4,-2))
io.out.word := pattern(List(13,-6,-4)).reduce(_&_) io.out.word := pattern(List(13,-6,-4))
io.out.csr_read := pattern(List(13,6,4)).reduce(_&_) | pattern(List(7,6,4)).reduce(_&_) | io.out.csr_read := pattern(List(13,6,4)) | pattern(List(7,6,4)) |
pattern(List(8,6,4)).reduce(_&_) | pattern(List(9,6,4)).reduce(_&_) | pattern(List(10,6,4)).reduce(_&_) | pattern(List(8,6,4)) | pattern(List(9,6,4)) | pattern(List(10,6,4)) |
pattern(List(11,6,4)).reduce(_&_) pattern(List(11,6,4))
io.out.csr_clr := pattern(List(15,13,12,6,4)).reduce(_&_) | pattern(List(16,13,12,6,4)).reduce(_&_) | io.out.csr_clr := pattern(List(15,13,12,6,4)) | pattern(List(16,13,12,6,4)) |
pattern(List(17,13,12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) | pattern(List(17,13,12,6,4)) | pattern(List(18,13,12,6,4)) |
pattern(List(19,-12,6,4)).reduce(_&_) pattern(List(19,13,12,6,4))
io.out.csr_write := pattern(List(-13,12,6,4)).reduce(_&_) io.out.csr_write := pattern(List(-13,12,6,4))
io.out.csr_imm := pattern(List(14,-13,6,4)).reduce(_&_) | pattern(List(15,14,6,4)).reduce(_&_) | io.out.csr_imm := pattern(List(14,-13,6,4)) | pattern(List(15,14,6,4)) |
pattern(List(16,14,6,4)).reduce(_&_) | pattern(List(17,14,6,4)).reduce(_&_) | pattern(List(16,14,6,4)) | pattern(List(17,14,6,4)) |
pattern(List(18,14,6,4)).reduce(_&_) | pattern(List(19,14,6,4)).reduce(_&_) pattern(List(18,14,6,4)) | pattern(List(19,14,6,4))
io.out.csr_set := pattern(List(15,-12,6,4)).reduce(_&_) | pattern(List(16,-12,6,4)).reduce(_&_) | io.out.csr_set := pattern(List(15,-12,6,4)) | pattern(List(16,-12,6,4)) |
pattern(List(17,-12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) | pattern(List(17,-12,6,4)) | pattern(List(18,-12,6,4)) |
pattern(List(19,-12,6,4)).reduce(_&_) pattern(List(19,-12,6,4))
io.out.ebreak := pattern(List(-22,20,-13,-12,6,4)).reduce(_&_) io.out.ebreak := pattern(List(-22,20,-13,-12,6,4))
io.out.ecall := pattern(List(-21,-20,-13,-12,6,4)).reduce(_&_) io.out.ecall := pattern(List(-21,-20,-13,-12,6,4))
io.out.mret := pattern(List(29,-13,-12,6,4)).reduce(_&_) io.out.mret := pattern(List(29,-13,-12,6,4))
io.out.mul := pattern(List(25,-14,-6,5,4,-2)).reduce(_&_) io.out.mul := pattern(List(25,-14,-6,5,4,-2))
io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)).reduce(_&_) | io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)) |
pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_) pattern(List(25,-14,-13,12,-6,4,-2))
io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_) io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2))
io.out.low := pattern(List(25,-14,-13,-12,5,4,-2)).reduce(_&_) io.out.low := pattern(List(25,-14,-13,-12,5,4,-2))
io.out.div := pattern(List(25,14,-6,5,-2)).reduce(_&_) io.out.div := pattern(List(25,14,-6,5,-2))
io.out.rem := pattern(List(25,14,13,-6,5,-2)).reduce(_&_) io.out.rem := pattern(List(25,14,13,-6,5,-2))
io.out.fence := pattern(List(-5,3)).reduce(_&_) io.out.fence := pattern(List(-5,3))
io.out.fence_i := pattern(List(12,-5,3)).reduce(_&_) io.out.fence_i := pattern(List(12,-5,3))
io.out.pm_alu := pattern(List(28,22,-13,-12,4)).reduce(_&_) | pattern(List(4,2)).reduce(_&_) | io.out.pm_alu := pattern(List(28,22,-13,-12,4)) | pattern(List(4,2)) |
pattern(List(-25,-6,4)).reduce(_&_) | pattern(List(-5,4)).reduce(_&_) pattern(List(-25,-6,4)) | pattern(List(-5,4))
io.out.presync := pattern(List(-5,3)).reduce(_&_) | pattern(List(-13,7,6,4)).reduce(_&_) | io.out.presync := pattern(List(-5,3)) | pattern(List(-13,7,6,4)) |
pattern(List(-13,8,6,4)).reduce(_&_) | pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,8,6,4)) | pattern(List(-13,9,6,4)) |
pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)) | pattern(List(-13,11,6,4)) |
pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) | pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) |
pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)) | pattern(List(18,13,6,4)) |
pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_) pattern(List(19,13,6,4))
io.out.postsync := pattern(List(12,-5,3)).reduce(_&_) | pattern(List(-22,-13,-12,6,4)).reduce(_&_) | io.out.postsync := pattern(List(12,-5,3)) | pattern(List(-22,-13,-12,6,4)) |
pattern(List(-13,7,6,4)).reduce(_&_) | pattern(List(-13,8,6,4)).reduce(_&_) | pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) |
pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) | pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) |
pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) | pattern(List(-13,11,6,4)) | pattern(List(15,13,6,4)) |
pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) | pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) |
pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_) pattern(List(18,13,6,4)) | pattern(List(19,13,6,4))
io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) | io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) |
pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) | pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)).reduce(_&_) | pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)).reduce(_&_) | pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)) |
pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)).reduce(_&_) | pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)) |
pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)).reduce(_&_) | pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)) |
pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)).reduce(_&_) | pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)) |
pattern(List(-14,-13,-12,6,5,-4,-3,1,0)).reduce(_&_) | pattern(List(-14,-13,-12,6,5,-4,-3,1,0)) |
pattern(List(14,6,5,-4,-3,-2,1,0)).reduce(_&_) | pattern(List(14,6,5,-4,-3,-2,1,0)) |
pattern(List(-12,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-13,5,-4,-3,-2,1,0)).reduce(_&_) | pattern(List(-12,-6,-5,4,-3,1,0)) |
pattern(List(12,6,5,4,-3,-2,1,0)).reduce(_&_) | pattern(List(-14,-13,5,-4,-3,-2,1,0)) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) | pattern(List(12,6,5,4,-3,-2,1,0)) |
pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) | pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) |
pattern(List(-13,-6,-5,-4,-3,-2,1,0)).reduce(_&_) | pattern(List(6,5,-4,3,2,1,0)).reduce(_&_) | pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) |
pattern(List(13,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-12,-6,-4,-3,-2,1,0)).reduce(_&_) | pattern(List(13,6,5,4,-3,-2,1,0)) |
pattern(List(-6,4,-3,-2,1,0)).reduce(_&_) pattern(List(-13,-6,-5,-4,-3,-2,1,0)) |
pattern(List(6,5,-4,3,2,1,0)) |
pattern(List(13,-6,-5,4,-3,1,0)) |
pattern(List(-14,-12,-6,-4,-3,-2,1,0)) |
pattern(List(-6,4,-3,2,1,0))
} }
//object dec extends App { object dec_dec_ctl extends App {
// println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_dec_ctl())) chisel3.Driver execute(args, () => new el2_dec_dec_ctl())
//} }

53
src/main/scala/dec/el2_dec_decode_ctl.scala
View File

@ -35,7 +35,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group
val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type
val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error
val dec_i0_brp = Flipped(Valid(new el2_br_pkt_t)) // branch packet val dec_i0_brp = Input(new el2_br_pkt_t) // branch packet
val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
@ -144,13 +144,13 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val i0_rs1_depth_d = WireInit(UInt(2.W),0.U) val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
val i0_rs2_depth_d = WireInit(UInt(2.W),0.U) val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t))) val cam = Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
val cam_write=WireInit(UInt(1.W), 0.U) val cam_write=WireInit(UInt(1.W), 0.U)
val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t))) val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t))) val cam_in =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
//val i0_temp = Wire(new el2_inst_pkt_t) //val i0_temp = Wire(new el2_inst_pkt_t)
val i0_dp= Wire(new el2_dec_pkt_t) val i0_dp= Wire(new el2_dec_pkt_t)
val i0_dp_raw= Wire(new el2_dec_pkt_t) val i0_dp_raw= Wire(new el2_dec_pkt_t)
@ -230,24 +230,24 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
io.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error io.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error
io.dec_i0_predict_p_d.bits.pja := i0_pja io.dec_i0_predict_p_d.bits.pja := i0_pja
io.dec_i0_predict_p_d.bits.pret := i0_pret io.dec_i0_predict_p_d.bits.pret := i0_pret
io.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett io.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.prett
io.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d io.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d
io.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist io.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.hist
io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d
val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw) val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
// no toffset error for a pret // no toffset error for a pret
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.hist(1) & (io.dec_i0_brp.toffset =/= i0_br_offset) & !i0_pret_raw
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw; val i0_ret_error = i0_brp_valid & io.dec_i0_brp.ret & !i0_pret_raw;
val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error val i0_br_error = io.dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
io.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode io.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode
io.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode io.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.br_start_error & i0_legal_decode_d & !leak1_mode
io.i0_predict_index_d := io.dec_i0_bp_index io.i0_predict_index_d := io.dec_i0_bp_index
io.i0_predict_btag_d := io.dec_i0_bp_btag io.i0_predict_btag_d := io.dec_i0_bp_btag
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode val i0_br_error_all = (i0_br_error | io.dec_i0_brp.br_start_error) & !leak1_mode
io.dec_i0_predict_p_d.bits.toffset := i0_br_offset io.dec_i0_predict_p_d.bits.toffset := i0_br_offset
io.i0_predict_fghr_d := io.dec_i0_bp_fghr io.i0_predict_fghr_d := io.dec_i0_bp_fghr
io.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way io.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.way
// end // end
// on br error turn anything into a nop // on br error turn anything into a nop
@ -273,8 +273,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
// branches that can be predicted // branches that can be predicted
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br val i0_predict_nt = !(io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br val i0_predict_t = (io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
val i0_ap_pc2 = !io.dec_i0_pc4_d val i0_ap_pc2 = !io.dec_i0_pc4_d
val i0_ap_pc4 = io.dec_i0_pc4_d val i0_ap_pc4 = io.dec_i0_pc4_d
io.i0_ap.predict_nt := i0_predict_nt io.i0_ap.predict_nt := i0_predict_nt
@ -318,8 +318,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)} val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)}
val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load
for(i <- 0 until LSU_NUM_NBLOAD){ for(i <- 0 until LSU_NUM_NBLOAD){
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).tag) & cam(i).valid
cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).tag) & cam_raw(i).valid
cam_in(i):=0.U.asTypeOf(cam(0)) cam_in(i):=0.U.asTypeOf(cam(0))
cam(i):=cam_raw(i) cam(i):=cam_raw(i)
@ -328,16 +328,16 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
} }
when(cam_wen(i).asBool){ when(cam_wen(i).asBool){
cam_in(i).valid := 1.U(1.W) cam_in(i).valid := 1.U(1.W)
cam_in(i).bits.wb := 0.U(1.W) cam_in(i).wb := 0.U(1.W)
cam_in(i).bits.tag := cam_write_tag cam_in(i).tag := cam_write_tag
cam_in(i).bits.rd := nonblock_load_rd cam_in(i).rd := nonblock_load_rd
}.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){ }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).rd) && cam(i).wb.asBool)){
cam_in(i).valid := 0.U cam_in(i).valid := 0.U
}.otherwise{ }.otherwise{
cam_in(i) := cam(i) cam_in(i) := cam(i)
} }
when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).bits.tag) && cam(i).valid===1.U){ when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).tag) && cam(i).valid===1.U){
cam_in(i).bits.wb := 1.U cam_in(i).wb := 1.U
} }
// force debug halt forces cam valids to 0; highest priority // force debug halt forces cam valids to 0; highest priority
when(io.dec_tlu_force_halt){ when(io.dec_tlu_force_halt){
@ -345,7 +345,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
} }
cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))} cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))}
nonblock_load_write(i) := (load_data_tag === cam_raw(i).bits.tag) & cam_raw(i).valid nonblock_load_write(i) := (load_data_tag === cam_raw(i).tag) & cam_raw(i).valid
} }
io.dec_nonblock_load_waddr:=0.U(5.W) io.dec_nonblock_load_waddr:=0.U(5.W)
@ -356,7 +356,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
i0_nonblock_load_stall := i0_nonblock_boundary_stall i0_nonblock_load_stall := i0_nonblock_boundary_stall
val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).bits.rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs2)) val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).rd === i0r.rs2))
val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) ) val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) )
io.dec_nonblock_load_waddr:=waddr io.dec_nonblock_load_waddr:=waddr
i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall
@ -819,6 +819,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
(!io.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20), (!io.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20),
(!io.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7)))) (!io.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7))))
} }
object decode_ctrl extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_decode_ctl())) object dec_decode extends App{
chisel3.Driver.emitVerilog(new el2_dec_decode_ctl)
} }

19
src/main/scala/dec/el2_dec_gpr_ctl.scala
View File

@ -5,14 +5,24 @@ import chisel3.util._
import include._ import include._
import lib._ import lib._
class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib { class el2_dec_gpr_ctl extends Module with el2_lib with RequireAsyncReset{
val io =IO(new el2_dec_gpr_ctl_IO) val io =IO(new el2_dec_gpr_ctl_IO)
val w0v =Wire(Vec(32,UInt(1.W))) val w0v =Wire(Vec(32,UInt(1.W)))
w0v := (0 until 32).map(i => 0.U)
val w1v =Wire(Vec(32,UInt(1.W))) val w1v =Wire(Vec(32,UInt(1.W)))
w1v := (0 until 32).map(i => 0.U)
val w2v =Wire(Vec(32,UInt(1.W))) val w2v =Wire(Vec(32,UInt(1.W)))
w2v := (0 until 32).map(i => 0.U)
val gpr_in =Wire(Vec(32,UInt(32.W))) val gpr_in =Wire(Vec(32,UInt(32.W)))
gpr_in := (0 until 32).map(i => 0.U)
val gpr_out =Wire(Vec(32,UInt(32.W))) val gpr_out =Wire(Vec(32,UInt(32.W)))
val gpr_wr_en =Wire(UInt(32.W)) gpr_out := (0 until 32).map(i => 0.U)
val gpr_wr_en =WireInit(UInt(32.W),0.U)
w0v(0):=0.U w0v(0):=0.U
w1v(0):=0.U w1v(0):=0.U
w2v(0):=0.U w2v(0):=0.U
@ -20,7 +30,6 @@ class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib {
gpr_in(0):=0.U gpr_in(0):=0.U
io.rd0:=0.U io.rd0:=0.U
io.rd1:=0.U io.rd1:=0.U
gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_))
// GPR Write logic // GPR Write logic
for (j <-1 until 32){ for (j <-1 until 32){
w0v(j) := io.wen0 & (io.waddr0===j.asUInt) w0v(j) := io.wen0 & (io.waddr0===j.asUInt)
@ -28,6 +37,8 @@ class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib {
w2v(j) := io.wen2 & (io.waddr2===j.asUInt) w2v(j) := io.wen2 & (io.waddr2===j.asUInt)
gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2) gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2)
} }
gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_))
// GPR Write Enables for power savings // GPR Write Enables for power savings
for (j <-1 until 32){ for (j <-1 until 32){
gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode) gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode)
@ -54,5 +65,5 @@ class el2_dec_gpr_ctl_IO extends Bundle{
val scan_mode=Input(Bool()) val scan_mode=Input(Bool())
} }
object gpr_gen extends App{ object gpr_gen extends App{
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_gpr_ctl))) println(chisel3.Driver.emitVerilog(new el2_dec_gpr_ctl))
} }

79
src/main/scala/dec/el2_dec_ib_ctl.scala
View File

@ -3,41 +3,6 @@ import include._
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import lib._ import lib._
class el2_dec_ib_ctl_IO extends Bundle with param{
val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd
val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write
val dbg_cmd_type =Input(UInt(2.W)) // dbg type
val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0
val i0_brp =Flipped(Valid(new el2_br_pkt_t)) // i0 branch packet from aligner
val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size)
val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR
val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag
val ifu_i0_pc4 =Input(UInt(1.W)) // i0 is 4B inst else 2B
val ifu_i0_valid =Input(UInt(1.W)) // i0 valid from ifu
val ifu_i0_icaf =Input(UInt(1.W)) // i0 instruction access fault
val ifu_i0_icaf_type =Input(UInt(2.W)) // i0 instruction access fault type
val ifu_i0_icaf_f1 =Input(UInt(1.W)) // i0 has access fault on second fetch group
val ifu_i0_dbecc =Input(UInt(1.W)) // i0 double-bit error
val ifu_i0_instr =Input(UInt(32.W)) // i0 instruction from the aligner
val ifu_i0_pc =Input(UInt(31.W)) // i0 pc from the aligner
val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid
val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type
val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode
val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode
val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B
val dec_i0_brp =Valid(new el2_br_pkt_t) // i0 branch packet at decode
val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR
val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag
val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode
val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group
val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode
val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted
val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst
}
class el2_dec_ib_ctl extends Module with param{ class el2_dec_ib_ctl extends Module with param{
val io=IO(new el2_dec_ib_ctl_IO) val io=IO(new el2_dec_ib_ctl_IO)
io.dec_i0_icaf_f1_d :=io.ifu_i0_icaf_f1 io.dec_i0_icaf_f1_d :=io.ifu_i0_icaf_f1
@ -46,7 +11,7 @@ class el2_dec_ib_ctl extends Module with param{
io.dec_i0_pc_d :=io.ifu_i0_pc io.dec_i0_pc_d :=io.ifu_i0_pc
io.dec_i0_pc4_d :=io.ifu_i0_pc4 io.dec_i0_pc4_d :=io.ifu_i0_pc4
io.dec_i0_icaf_type_d :=io.ifu_i0_icaf_type io.dec_i0_icaf_type_d :=io.ifu_i0_icaf_type
io.dec_i0_brp <>io.i0_brp io.dec_i0_brp :=io.i0_brp
io.dec_i0_bp_index :=io.ifu_i0_bp_index io.dec_i0_bp_index :=io.ifu_i0_bp_index
io.dec_i0_bp_fghr :=io.ifu_i0_bp_fghr io.dec_i0_bp_fghr :=io.ifu_i0_bp_fghr
io.dec_i0_bp_btag :=io.ifu_i0_bp_btag io.dec_i0_bp_btag :=io.ifu_i0_bp_btag
@ -77,9 +42,9 @@ class el2_dec_ib_ctl extends Module with param{
val ib0_debug_in =Mux1H(Seq( val ib0_debug_in =Mux1H(Seq(
debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U), debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U),
debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)), debug_write_gpr.asBool -> Cat("b00000000000000000110".U,dreg,"b0110011".U),
debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)), debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U),
debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W)) debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U)
)) ))
// machine is in halted state, pipe empty, write will always happen next cycle // machine is in halted state, pipe empty, write will always happen next cycle
@ -93,7 +58,39 @@ class el2_dec_ib_ctl extends Module with param{
} }
class el2_dec_ib_ctl_IO extends Bundle with param{
val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd
val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write
val dbg_cmd_type =Input(UInt(2.W)) // dbg type
val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0
val i0_brp =Input(new el2_br_pkt_t) // i0 branch packet from aligner
val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size)
val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR
val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag
val ifu_i0_pc4 =Input(UInt(1.W)) // i0 is 4B inst else 2B
val ifu_i0_valid =Input(UInt(1.W)) // i0 valid from ifu
val ifu_i0_icaf =Input(UInt(1.W)) // i0 instruction access fault
val ifu_i0_icaf_type =Input(UInt(2.W)) // i0 instruction access fault type
val ifu_i0_icaf_f1 =Input(UInt(1.W)) // i0 has access fault on second fetch group
val ifu_i0_dbecc =Input(UInt(1.W)) // i0 double-bit error
val ifu_i0_instr =Input(UInt(32.W)) // i0 instruction from the aligner
val ifu_i0_pc =Input(UInt(31.W)) // i0 pc from the aligner
object ib_gen extends App{ val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_ib_ctl))) val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type
val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode
val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode
val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B
val dec_i0_brp =Output(new el2_br_pkt_t) // i0 branch packet at decode
val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR
val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag
val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode
val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group
val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode
val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted
val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst
}
object ib_gen extends App{
chisel3.Driver.emitVerilog(new el2_dec_ib_ctl)
} }

282
src/main/scala/dec/el2_dec_tlu_ctl.scala
View File

@ -188,7 +188,7 @@ class el2_dec_tlu_ctl_IO extends Bundle with el2_lib {
val dec_tlu_meipt = Output(UInt(4.W)) // to PIC val dec_tlu_meipt = Output(UInt(4.W)) // to PIC
val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb
val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation
val dec_tlu_br0_r_pkt = Valid(new el2_br_tlu_pkt_t) // branch pkt to bp val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // branch pkt to bp
val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state
val dec_tlu_flush_lower_wb = Output(UInt(1.W)) // commit has a flush (exception, int, mispredict at e4) val dec_tlu_flush_lower_wb = Output(UInt(1.W)) // commit has a flush (exception, int, mispredict at e4)
val dec_tlu_i0_commit_cmt = Output(UInt(1.W)) // committed an instruction val dec_tlu_i0_commit_cmt = Output(UInt(1.W)) // committed an instruction
@ -234,122 +234,122 @@ class el2_dec_tlu_ctl_IO extends Bundle with el2_lib {
class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CSR_VAL{ class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CSR_VAL{
val io = IO(new el2_dec_tlu_ctl_IO) val io = IO(new el2_dec_tlu_ctl_IO)
val mtdata1_t = Wire(Vec(4,UInt(10.W))) val mtdata1_t = Wire(Vec(4,UInt(10.W)))
val pause_expired_wb =Wire(UInt(1.W)) val pause_expired_wb =WireInit(UInt(1.W), 0.U)
val take_nmi_r_d1 =Wire(UInt(1.W)) val take_nmi_r_d1 =WireInit(UInt(1.W),0.U)
val exc_or_int_valid_r_d1 =Wire(UInt(1.W)) val exc_or_int_valid_r_d1 =WireInit(UInt(1.W),0.U)
val interrupt_valid_r_d1 =Wire(UInt(1.W)) val interrupt_valid_r_d1 =WireInit(UInt(1.W),0.U)
val tlu_flush_lower_r =Wire(UInt(1.W)) val tlu_flush_lower_r =WireInit(UInt(1.W),0.U)
val synchronous_flush_r =Wire(UInt(1.W)) val synchronous_flush_r =WireInit(UInt(1.W),0.U)
val interrupt_valid_r =Wire(UInt(1.W)) val interrupt_valid_r =WireInit(UInt(1.W),0.U)
val take_nmi =Wire(UInt(1.W)) val take_nmi =WireInit(UInt(1.W),0.U)
val take_reset =Wire(UInt(1.W)) val take_reset =WireInit(UInt(1.W),0.U)
val take_int_timer1_int =Wire(UInt(1.W)) val take_int_timer1_int =WireInit(UInt(1.W),0.U)
val take_int_timer0_int =Wire(UInt(1.W)) val take_int_timer0_int =WireInit(UInt(1.W),0.U)
val take_timer_int =Wire(UInt(1.W)) val take_timer_int =WireInit(UInt(1.W),0.U)
val take_soft_int =Wire(UInt(1.W)) val take_soft_int =WireInit(UInt(1.W),0.U)
val take_ce_int =Wire(UInt(1.W)) val take_ce_int =WireInit(UInt(1.W),0.U)
val take_ext_int_start =Wire(UInt(1.W)) val take_ext_int_start =WireInit(UInt(1.W),0.U)
val ext_int_freeze =Wire(UInt(1.W)) val ext_int_freeze =WireInit(UInt(1.W),0.U)
val ext_int_freeze_d1 =Wire(UInt(1.W)) val ext_int_freeze_d1 =WireInit(UInt(1.W),0.U)
val take_ext_int_start_d1 =Wire(UInt(1.W)) val take_ext_int_start_d1 =WireInit(UInt(1.W),0.U)
val take_ext_int_start_d2 =Wire(UInt(1.W)) val take_ext_int_start_d2 =WireInit(UInt(1.W),0.U)
val take_ext_int_start_d3 =Wire(UInt(1.W)) val take_ext_int_start_d3 =WireInit(UInt(1.W),0.U)
val fast_int_meicpct =Wire(UInt(1.W)) val fast_int_meicpct =WireInit(UInt(1.W),0.U)
val ignore_ext_int_due_to_lsu_stall =Wire(UInt(1.W)) val ignore_ext_int_due_to_lsu_stall =WireInit(UInt(1.W),0.U)
val take_ext_int =Wire(UInt(1.W)) val take_ext_int =WireInit(UInt(1.W),0.U)
val internal_dbg_halt_timers =Wire(UInt(1.W)) val internal_dbg_halt_timers =WireInit(UInt(1.W),0.U)
val int_timer1_int_hold =Wire(UInt(1.W)) val int_timer1_int_hold =WireInit(UInt(1.W),0.U)
val int_timer0_int_hold =Wire(UInt(1.W)) val int_timer0_int_hold =WireInit(UInt(1.W),0.U)
val mhwakeup_ready =Wire(UInt(1.W)) val mhwakeup_ready =WireInit(UInt(1.W),0.U)
val ext_int_ready =Wire(UInt(1.W)) val ext_int_ready =WireInit(UInt(1.W),0.U)
val ce_int_ready =Wire(UInt(1.W)) val ce_int_ready =WireInit(UInt(1.W),0.U)
val soft_int_ready =Wire(UInt(1.W)) val soft_int_ready =WireInit(UInt(1.W),0.U)
val timer_int_ready =Wire(UInt(1.W)) val timer_int_ready =WireInit(UInt(1.W),0.U)
val ebreak_to_debug_mode_r_d1 =Wire(UInt(1.W)) val ebreak_to_debug_mode_r_d1 =WireInit(UInt(1.W),0.U)
val ebreak_to_debug_mode_r =Wire(UInt(1.W)) val ebreak_to_debug_mode_r =WireInit(UInt(1.W),0.U)
val inst_acc_r =Wire(UInt(1.W)) val inst_acc_r =WireInit(UInt(1.W),0.U)
val inst_acc_r_raw =Wire(UInt(1.W)) val inst_acc_r_raw =WireInit(UInt(1.W),0.U)
val iccm_sbecc_r =Wire(UInt(1.W)) val iccm_sbecc_r =WireInit(UInt(1.W),0.U)
val ic_perr_r =Wire(UInt(1.W)) val ic_perr_r =WireInit(UInt(1.W),0.U)
val fence_i_r =Wire(UInt(1.W)) val fence_i_r =WireInit(UInt(1.W),0.U)
val ebreak_r =Wire(UInt(1.W)) val ebreak_r =WireInit(UInt(1.W),0.U)
val ecall_r =Wire(UInt(1.W)) val ecall_r =WireInit(UInt(1.W),0.U)
val illegal_r =Wire(UInt(1.W)) val illegal_r =WireInit(UInt(1.W),0.U)
val mret_r =Wire(UInt(1.W)) val mret_r =WireInit(UInt(1.W),0.U)
val iccm_repair_state_ns =Wire(UInt(1.W)) val iccm_repair_state_ns =WireInit(UInt(1.W),0.U)
val rfpc_i0_r =Wire(UInt(1.W)) val rfpc_i0_r =WireInit(UInt(1.W),0.U)
val tlu_i0_kill_writeb_r =Wire(UInt(1.W)) val tlu_i0_kill_writeb_r =WireInit(UInt(1.W),0.U)
val lsu_exc_valid_r_d1 =Wire(UInt(1.W)) val lsu_exc_valid_r_d1 =WireInit(UInt(1.W),0.U)
val lsu_i0_exc_r_raw =Wire(UInt(1.W)) val lsu_i0_exc_r_raw =WireInit(UInt(1.W),0.U)
val mdseac_locked_f =Wire(UInt(1.W)) val mdseac_locked_f =WireInit(UInt(1.W),0.U)
val i_cpu_run_req_d1 =Wire(UInt(1.W)) val i_cpu_run_req_d1 =WireInit(UInt(1.W),0.U)
val cpu_run_ack =Wire(UInt(1.W)) val cpu_run_ack =WireInit(UInt(1.W),0.U)
val cpu_halt_status =Wire(UInt(1.W)) val cpu_halt_status =WireInit(UInt(1.W),0.U)
val cpu_halt_ack =Wire(UInt(1.W)) val cpu_halt_ack =WireInit(UInt(1.W),0.U)
val pmu_fw_tlu_halted =Wire(UInt(1.W)) val pmu_fw_tlu_halted =WireInit(UInt(1.W),0.U)
val internal_pmu_fw_halt_mode =Wire(UInt(1.W)) val internal_pmu_fw_halt_mode =WireInit(UInt(1.W),0.U)
val pmu_fw_halt_req_ns =Wire(UInt(1.W)) val pmu_fw_halt_req_ns =WireInit(UInt(1.W),0.U)
val pmu_fw_halt_req_f =Wire(UInt(1.W)) val pmu_fw_halt_req_f =WireInit(UInt(1.W),0.U)
val pmu_fw_tlu_halted_f =Wire(UInt(1.W)) val pmu_fw_tlu_halted_f =WireInit(UInt(1.W),0.U)
val int_timer0_int_hold_f =Wire(UInt(1.W)) val int_timer0_int_hold_f =WireInit(UInt(1.W),0.U)
val int_timer1_int_hold_f =Wire(UInt(1.W)) val int_timer1_int_hold_f =WireInit(UInt(1.W),0.U)
val trigger_hit_dmode_r =Wire(UInt(1.W)) val trigger_hit_dmode_r =WireInit(UInt(1.W),0.U)
val i0_trigger_hit_r =Wire(UInt(1.W)) val i0_trigger_hit_r =WireInit(UInt(1.W),0.U)
val pause_expired_r =Wire(UInt(1.W)) val pause_expired_r =WireInit(UInt(1.W),0.U)
val dec_tlu_pmu_fw_halted =Wire(UInt(1.W)) val dec_tlu_pmu_fw_halted =WireInit(UInt(1.W),0.U)
val dec_tlu_flush_noredir_r_d1 =Wire(UInt(1.W)) val dec_tlu_flush_noredir_r_d1 =WireInit(UInt(1.W),0.U)
val halt_taken_f =Wire(UInt(1.W)) val halt_taken_f =WireInit(UInt(1.W),0.U)
val lsu_idle_any_f =Wire(UInt(1.W)) val lsu_idle_any_f =WireInit(UInt(1.W),0.U)
val ifu_miss_state_idle_f =Wire(UInt(1.W)) val ifu_miss_state_idle_f =WireInit(UInt(1.W),0.U)
val dbg_tlu_halted_f =Wire(UInt(1.W)) val dbg_tlu_halted_f =WireInit(UInt(1.W),0.U)
val debug_halt_req_f =Wire(UInt(1.W)) val debug_halt_req_f =WireInit(UInt(1.W),0.U)
val debug_resume_req_f =Wire(UInt(1.W)) val debug_resume_req_f =WireInit(UInt(1.W),0.U)
val trigger_hit_dmode_r_d1 =Wire(UInt(1.W)) val trigger_hit_dmode_r_d1 =WireInit(UInt(1.W),0.U)
val dcsr_single_step_done_f =Wire(UInt(1.W)) val dcsr_single_step_done_f =WireInit(UInt(1.W),0.U)
val debug_halt_req_d1 =Wire(UInt(1.W)) val debug_halt_req_d1 =WireInit(UInt(1.W),0.U)
val request_debug_mode_r_d1 =Wire(UInt(1.W)) val request_debug_mode_r_d1 =WireInit(UInt(1.W),0.U)
val request_debug_mode_done_f =Wire(UInt(1.W)) val request_debug_mode_done_f =WireInit(UInt(1.W),0.U)
val dcsr_single_step_running_f =Wire(UInt(1.W)) val dcsr_single_step_running_f =WireInit(UInt(1.W),0.U)
val dec_tlu_flush_pause_r_d1 =Wire(UInt(1.W)) val dec_tlu_flush_pause_r_d1 =WireInit(UInt(1.W),0.U)
val dbg_halt_req_held =Wire(UInt(1.W)) val dbg_halt_req_held =WireInit(UInt(1.W),0.U)
val debug_halt_req_ns =Wire(UInt(1.W)) val debug_halt_req_ns =WireInit(UInt(1.W),0.U)
val internal_dbg_halt_mode =Wire(UInt(1.W)) val internal_dbg_halt_mode =WireInit(UInt(1.W),0.U)
val core_empty =Wire(UInt(1.W)) val core_empty =WireInit(UInt(1.W),0.U)
val dbg_halt_req_final =Wire(UInt(1.W)) val dbg_halt_req_final =WireInit(UInt(1.W),0.U)
val debug_brkpt_status_ns =Wire(UInt(1.W)) val debug_brkpt_status_ns =WireInit(UInt(1.W),0.U)
val mpc_debug_halt_ack_ns =Wire(UInt(1.W)) val mpc_debug_halt_ack_ns =WireInit(UInt(1.W),0.U)
val mpc_debug_run_ack_ns =Wire(UInt(1.W)) val mpc_debug_run_ack_ns =WireInit(UInt(1.W),0.U)
val mpc_halt_state_ns =Wire(UInt(1.W)) val mpc_halt_state_ns =WireInit(UInt(1.W),0.U)
val mpc_run_state_ns =Wire(UInt(1.W)) val mpc_run_state_ns =WireInit(UInt(1.W),0.U)
val dbg_halt_state_ns =Wire(UInt(1.W)) val dbg_halt_state_ns =WireInit(UInt(1.W),0.U)
val dbg_run_state_ns =Wire(UInt(1.W)) val dbg_run_state_ns =WireInit(UInt(1.W),0.U)
val dbg_halt_state_f =Wire(UInt(1.W)) val dbg_halt_state_f =WireInit(UInt(1.W),0.U)
val mpc_halt_state_f =Wire(UInt(1.W)) val mpc_halt_state_f =WireInit(UInt(1.W),0.U)
val nmi_int_detected =Wire(UInt(1.W)) val nmi_int_detected =WireInit(UInt(1.W),0.U)
val nmi_lsu_load_type =Wire(UInt(1.W)) val nmi_lsu_load_type =WireInit(UInt(1.W),0.U)
val nmi_lsu_store_type =Wire(UInt(1.W)) val nmi_lsu_store_type =WireInit(UInt(1.W),0.U)
val reset_delayed =Wire(UInt(1.W)) val reset_delayed =WireInit(UInt(1.W),0.U)
val internal_dbg_halt_mode_f =Wire(UInt(1.W)) val internal_dbg_halt_mode_f =WireInit(UInt(1.W),0.U)
val e5_valid =Wire(UInt(1.W)) val e5_valid =WireInit(UInt(1.W),0.U)
val ic_perr_r_d1 =Wire(UInt(1.W)) val ic_perr_r_d1 =WireInit(UInt(1.W),0.U)
val iccm_sbecc_r_d1 =Wire(UInt(1.W)) val iccm_sbecc_r_d1 =WireInit(UInt(1.W),0.U)
val npc_r = Wire(UInt(31.W)) val npc_r = WireInit(UInt(31.W),0.U)
val npc_r_d1 = Wire(UInt(31.W)) val npc_r_d1 = WireInit(UInt(31.W),0.U)
val mie_ns = Wire(UInt(6.W)) val mie_ns = WireInit(UInt(6.W),0.U)
val mepc = Wire(UInt(31.W)) val mepc = WireInit(UInt(31.W),0.U)
val mdseac_locked_ns = Wire(UInt(1.W)) val mdseac_locked_ns = WireInit(UInt(1.W),0.U)
val force_halt = Wire(UInt(1.W)) val force_halt = WireInit(UInt(1.W),0.U)
val dpc = Wire(UInt(31.W)) val dpc = WireInit(UInt(31.W),0.U)
val mstatus_mie_ns = Wire(UInt(1.W)) val mstatus_mie_ns = WireInit(UInt(1.W),0.U)
val dec_csr_wen_r_mod = Wire(UInt(1.W)) val dec_csr_wen_r_mod = WireInit(UInt(1.W),0.U)
val fw_halt_req = Wire(UInt(1.W)) val fw_halt_req = WireInit(UInt(1.W),0.U)
val mstatus = Wire(UInt(2.W)) val mstatus = WireInit(UInt(2.W),0.U)
val dcsr = Wire(UInt(16.W)) val dcsr = WireInit(UInt(16.W),0.U)
val mtvec = Wire(UInt(31.W)) val mtvec = WireInit(UInt(31.W),0.U)
val mip = Wire(UInt(6.W)) val mip = WireInit(UInt(6.W),0.U)
val csr_pkt = Wire(new el2_dec_tlu_csr_pkt) val csr_pkt = Wire(new el2_dec_tlu_csr_pkt)
val dec_tlu_mpc_halted_only_ns = Wire(UInt(1.W)) val dec_tlu_mpc_halted_only_ns = WireInit(UInt(1.W),0.U)
// tell dbg we are only MPC halted // tell dbg we are only MPC halted
dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f
val int_timers=Module(new el2_dec_timer_ctl) val int_timers=Module(new el2_dec_timer_ctl)
@ -692,7 +692,7 @@ class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CS
val lsu_exc_valid_r = lsu_i0_exc_r val lsu_exc_valid_r = lsu_i0_exc_r
lsu_exc_valid_r_d1 :=withClock(lsu_r_wb_clk){RegNext(lsu_exc_valid_r,0.U)} lsu_exc_valid_r_d1 :=withClock(lsu_r_wb_clk){RegNext(lsu_exc_valid_r,0.U)}
val lsu_i0_exc_r_d1 =withClock(lsu_r_wb_clk){RegNext(lsu_i0_exc_r,0.U)} val lsu_i0_exc_r_d1 =withClock(lsu_r_wb_clk){RegNext(lsu_i0_exc_r,0.U)}
val lsu_exc_ma_r = lsu_i0_exc_r & !io.lsu_error_pkt_r.bits.exc_type val lsu_exc_ma_r = lsu_i0_exc_r & ~io.lsu_error_pkt_r.bits.exc_type
val lsu_exc_acc_r = lsu_i0_exc_r & io.lsu_error_pkt_r.bits.exc_type val lsu_exc_acc_r = lsu_i0_exc_r & io.lsu_error_pkt_r.bits.exc_type
val lsu_exc_st_r = lsu_i0_exc_r & io.lsu_error_pkt_r.bits.inst_type val lsu_exc_st_r = lsu_i0_exc_r & io.lsu_error_pkt_r.bits.inst_type
@ -727,12 +727,12 @@ class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CS
val dec_tlu_br0_v_r = io.exu_i0_br_valid_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~io.exu_i0_br_mp_r | ~io.exu_pmu_i0_br_ataken) val dec_tlu_br0_v_r = io.exu_i0_br_valid_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~io.exu_i0_br_mp_r | ~io.exu_pmu_i0_br_ataken)
io.dec_tlu_br0_r_pkt.bits.hist := io.exu_i0_br_hist_r io.dec_tlu_br0_r_pkt.hist := io.exu_i0_br_hist_r
io.dec_tlu_br0_r_pkt.bits.br_error := dec_tlu_br0_error_r io.dec_tlu_br0_r_pkt.br_error := dec_tlu_br0_error_r
io.dec_tlu_br0_r_pkt.bits.br_start_error := dec_tlu_br0_start_error_r io.dec_tlu_br0_r_pkt.br_start_error := dec_tlu_br0_start_error_r
io.dec_tlu_br0_r_pkt.valid := dec_tlu_br0_v_r io.dec_tlu_br0_r_pkt.valid := dec_tlu_br0_v_r
io.dec_tlu_br0_r_pkt.bits.way := io.exu_i0_br_way_r io.dec_tlu_br0_r_pkt.way := io.exu_i0_br_way_r
io.dec_tlu_br0_r_pkt.bits.middle := io.exu_i0_br_middle_r io.dec_tlu_br0_r_pkt.middle := io.exu_i0_br_middle_r
ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r
@ -1447,16 +1447,16 @@ class el2_CSR_IO extends Bundle with el2_lib {
val mtdata1_t = Output(Vec(4,UInt(10.W))) val mtdata1_t = Output(Vec(4,UInt(10.W)))
} }
class csr_tlu extends Module with el2_lib with CSRs { class csr_tlu extends Module with el2_lib with CSRs with RequireAsyncReset {
val io = IO(new el2_CSR_IO) val io = IO(new el2_CSR_IO)
////////////////////////////////wires/////////////////////////////// ////////////////////////////////wires///////////////////////////////
val miccme_ce_req = Wire(UInt(1.W)) val miccme_ce_req = WireInit(UInt(1.W),0.U)
val mice_ce_req = Wire(UInt(1.W)) val mice_ce_req = WireInit(UInt(1.W),0.U)
val mdccme_ce_req = Wire(UInt(1.W)) val mdccme_ce_req = WireInit(UInt(1.W),0.U)
val pc_r_d1 = Wire(UInt(31.W)) val pc_r_d1 = WireInit(UInt(31.W),0.U)
val mpmc_b_ns = Wire(UInt(1.W)) val mpmc_b_ns = WireInit(UInt(1.W),0.U)
val mpmc_b = Wire(UInt(1.W)) val mpmc_b = WireInit(UInt(1.W),0.U)
val wr_mcycleh_r = WireInit(UInt(1.W), 0.U) val wr_mcycleh_r = WireInit(UInt(1.W), 0.U)
val mcycleh = WireInit(UInt(32.W),0.U) val mcycleh = WireInit(UInt(32.W),0.U)
val minstretl_inc = WireInit(UInt(33.W),0.U) val minstretl_inc = WireInit(UInt(33.W),0.U)
@ -2306,7 +2306,7 @@ class csr_tlu extends Module with el2_lib with CSRs {
val mtdata1_tsel_out = Mux1H((0 until 4).map(i => (mtsel === i.U(2.W)) -> Cat(2.U(4.W), io.mtdata1_t(i)(9), "b011111".U(6.W), io.mtdata1_t(i)(8,7), 0.U(6.W), io.mtdata1_t(i)(6,5), 0.U(3.W), io.mtdata1_t(i)(4,3), 0.U(3.W), io.mtdata1_t(i)(2,0)))) val mtdata1_tsel_out = Mux1H((0 until 4).map(i => (mtsel === i.U(2.W)) -> Cat(2.U(4.W), io.mtdata1_t(i)(9), "b011111".U(6.W), io.mtdata1_t(i)(8,7), 0.U(6.W), io.mtdata1_t(i)(6,5), 0.U(3.W), io.mtdata1_t(i)(4,3), 0.U(3.W), io.mtdata1_t(i)(2,0))))
for(i <- 0 until 4 ){ for(i <- 0 until 4 ){
io.trigger_pkt_any(i).select := io.mtdata1_t(i)(MTDATA1_SEL) io.trigger_pkt_any(i).select := io.mtdata1_t(i)(MTDATA1_SEL)
io.trigger_pkt_any(i).match_ := io.mtdata1_t(i)(MTDATA1_MATCH) io.trigger_pkt_any(i).match_pkt := io.mtdata1_t(i)(MTDATA1_MATCH)
io.trigger_pkt_any(i).store := io.mtdata1_t(i)(MTDATA1_ST) io.trigger_pkt_any(i).store := io.mtdata1_t(i)(MTDATA1_ST)
io.trigger_pkt_any(i).load := io.mtdata1_t(i)(MTDATA1_LD) io.trigger_pkt_any(i).load := io.mtdata1_t(i)(MTDATA1_LD)
io.trigger_pkt_any(i).execute := io.mtdata1_t(i)(MTDATA1_EXE) io.trigger_pkt_any(i).execute := io.mtdata1_t(i)(MTDATA1_EXE)
@ -2637,12 +2637,12 @@ class csr_tlu extends Module with el2_lib with CSRs {
} }
class el2_dec_decode_csr_read_IO extends Bundle with el2_lib { class el2_dec_decode_csr_read_IO extends Bundle{
val dec_csr_rdaddr_d=Input(UInt(12.W)) val dec_csr_rdaddr_d=Input(UInt(12.W))
val csr_pkt=Output(new el2_dec_tlu_csr_pkt) val csr_pkt=Output(new el2_dec_tlu_csr_pkt)
} }
class el2_dec_decode_csr_read extends Module with el2_lib { class el2_dec_decode_csr_read extends Module with RequireAsyncReset{
val io=IO(new el2_dec_decode_csr_read_IO) val io=IO(new el2_dec_decode_csr_read_IO)
def pattern(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0 & y(i)!='z') io.dec_csr_rdaddr_d(y(i)) else if(y(i)<0) !io.dec_csr_rdaddr_d(y(i).abs) else !io.dec_csr_rdaddr_d(0)).reduce(_&_) def pattern(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0 & y(i)!='z') io.dec_csr_rdaddr_d(y(i)) else if(y(i)<0) !io.dec_csr_rdaddr_d(y(i).abs) else !io.dec_csr_rdaddr_d(0)).reduce(_&_)
@ -2736,18 +2736,18 @@ class el2_dec_decode_csr_read extends Module with el2_lib {
} }
class el2_dec_timer_ctl extends Module with el2_lib { class el2_dec_timer_ctl extends Module with el2_lib with RequireAsyncReset{
val io=IO(new el2_dec_timer_ctl_IO) val io=IO(new el2_dec_timer_ctl_IO)
val MITCTL_ENABLE=0 val MITCTL_ENABLE=0
val MITCTL_ENABLE_HALTED=1 val MITCTL_ENABLE_HALTED=1
val MITCTL_ENABLE_PAUSED=2 val MITCTL_ENABLE_PAUSED=2
val mitctl1=Wire(UInt(4.W)) val mitctl1=WireInit(UInt(4.W),0.U)
val mitctl0=Wire(UInt(3.W)) val mitctl0=WireInit(UInt(3.W),0.U)
val mitb1 =Wire(UInt(32.W)) val mitb1 =WireInit(UInt(32.W),0.U)
val mitb0 =Wire(UInt(32.W)) val mitb0 =WireInit(UInt(32.W),0.U)
val mitcnt1=Wire(UInt(32.W)) val mitcnt1=WireInit(UInt(32.W),0.U)
val mitcnt0=Wire(UInt(32.W)) val mitcnt0=WireInit(UInt(32.W),0.U)
val mit0_match_ns=(mitcnt0 >= mitb0).asUInt val mit0_match_ns=(mitcnt0 >= mitb0).asUInt
val mit1_match_ns=(mitcnt1 >= mitb1).asUInt val mit1_match_ns=(mitcnt1 >= mitb1).asUInt
@ -2765,7 +2765,7 @@ class el2_dec_timer_ctl extends Module with el2_lib {
val mitcnt0_inc_ok = mitctl0(MITCTL_ENABLE) & (~io.dec_pause_state | mitctl0(MITCTL_ENABLE_PAUSED)) & (~io.dec_tlu_pmu_fw_halted | mitctl0(MITCTL_ENABLE_HALTED)) & ~io.internal_dbg_halt_timers val mitcnt0_inc_ok = mitctl0(MITCTL_ENABLE) & (~io.dec_pause_state | mitctl0(MITCTL_ENABLE_PAUSED)) & (~io.dec_tlu_pmu_fw_halted | mitctl0(MITCTL_ENABLE_HALTED)) & ~io.internal_dbg_halt_timers
val mitcnt0_inc = mitcnt0 + 1.U(32.W) val mitcnt0_inc = mitcnt0 + 1.U(32.W)
val mitcnt0_ns =Mux(mit0_match_ns.asBool, 0.U, Mux(wr_mitcnt0_r.asBool, io.dec_csr_wrdata_r, mitcnt0_inc)) val mitcnt0_ns =Mux(mit0_match_ns.asBool, 0.U, Mux(wr_mitcnt0_r.asBool, io.dec_csr_wrdata_r, mitcnt0_inc))
mitcnt0 := rvdffe(mitcnt0_ns,(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns).asBool,clock,io.scan_mode) mitcnt0 :=rvdffe(mitcnt0_ns,(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns).asBool,clock,io.scan_mode)
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
// MITCNT1 (RW) // MITCNT1 (RW)
@ -2796,7 +2796,7 @@ class el2_dec_timer_ctl extends Module with el2_lib {
val MITB1 =0x7d6.U(12.W) val MITB1 =0x7d6.U(12.W)
val wr_mitb1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r=== MITB1) val wr_mitb1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r=== MITB1)
val mitb1_b = rvdffe(~io.dec_csr_wrdata_r,wr_mitb1_r.asBool,clock,io.scan_mode) val mitb1_b=rvdffe((~io.dec_csr_wrdata_r),wr_mitb1_r.asBool,clock,io.scan_mode)
mitb1 := ~mitb1_b mitb1 := ~mitb1_b
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
@ -2868,5 +2868,5 @@ class el2_dec_timer_ctl_IO extends Bundle{
} }
object tlu_gen extends App{ object tlu_gen extends App{
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_tlu_ctl()))) println(chisel3.Driver.emitVerilog(new el2_dec_tlu_ctl))
} }

4
src/main/scala/dec/el2_dec_trigger.scala
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@ -12,9 +12,9 @@ class el2_dec_trigger extends Module with el2_lib {
val dec_i0_trigger_match_d = Output(UInt(4.W)) val dec_i0_trigger_match_d = Output(UInt(4.W))
}) })
val dec_i0_match_data = VecInit.tabulate(4)(i => repl(32, (!io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).execute)) & Cat(io.dec_i0_pc_d, io.trigger_pkt_any(i).tdata2(0))) val dec_i0_match_data = VecInit.tabulate(4)(i => repl(32, (!io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).execute)) & Cat(io.dec_i0_pc_d, io.trigger_pkt_any(i).tdata2(0)))
io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_.asBool())).reverse.reduce(Cat(_,_)) io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_pkt.asBool())).reverse.reduce(Cat(_,_))
} }
object dec_trig extends App { object dec_trig extends App {
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_trigger()))) chisel3.Driver execute(args, () => new el2_dec_trigger())
} }

2
src/main/scala/el2_swerv.scala
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@ -384,7 +384,7 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
ifu.io.exu_mp_fghr := exu.io.exu_mp_fghr ifu.io.exu_mp_fghr := exu.io.exu_mp_fghr
ifu.io.exu_mp_index := exu.io.exu_mp_index ifu.io.exu_mp_index := exu.io.exu_mp_index
ifu.io.exu_mp_btag := exu.io.exu_mp_btag ifu.io.exu_mp_btag := exu.io.exu_mp_btag
ifu.io.dec_tlu_br0_r_pkt <> dec.io.dec_tlu_br0_r_pkt ifu.io.dec_tlu_br0_r_pkt := dec.io.dec_tlu_br0_r_pkt
ifu.io.exu_i0_br_fghr_r := exu.io.exu_i0_br_fghr_r ifu.io.exu_i0_br_fghr_r := exu.io.exu_i0_br_fghr_r
ifu.io.exu_i0_br_index_r := exu.io.exu_i0_br_index_r ifu.io.exu_i0_br_index_r := exu.io.exu_i0_br_index_r
ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_tlu_flush_lower_r ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_tlu_flush_lower_r

6
src/main/scala/ifu/el2_ifu.scala
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@ -122,7 +122,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
val ifu_i0_pc4 = Output(Bool()) val ifu_i0_pc4 = Output(Bool())
val ifu_miss_state_idle = Output(Bool()) val ifu_miss_state_idle = Output(Bool())
// Aligner branch data // Aligner branch data
val i0_brp = Valid(new el2_br_pkt_t) val i0_brp = Output(new el2_br_pkt_t)
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W)) val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W)) val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
@ -132,7 +132,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W)) val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W))
val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index
val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W)) val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W))
val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t)) val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t)
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_lower_wb = Input(Bool())
@ -195,7 +195,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
bp_ctl_ch.io.ic_hit_f := mem_ctl_ch.io.ic_hit_f bp_ctl_ch.io.ic_hit_f := mem_ctl_ch.io.ic_hit_f
bp_ctl_ch.io.ifc_fetch_addr_f := ifc_ctl_ch.io.ifc_fetch_addr_f bp_ctl_ch.io.ifc_fetch_addr_f := ifc_ctl_ch.io.ifc_fetch_addr_f
bp_ctl_ch.io.ifc_fetch_req_f := ifc_ctl_ch.io.ifc_fetch_req_f bp_ctl_ch.io.ifc_fetch_req_f := ifc_ctl_ch.io.ifc_fetch_req_f
bp_ctl_ch.io.dec_tlu_br0_r_pkt <> io.dec_tlu_br0_r_pkt bp_ctl_ch.io.dec_tlu_br0_r_pkt := io.dec_tlu_br0_r_pkt
bp_ctl_ch.io.exu_i0_br_fghr_r := io.exu_i0_br_fghr_r bp_ctl_ch.io.exu_i0_br_fghr_r := io.exu_i0_br_fghr_r
bp_ctl_ch.io.exu_i0_br_index_r := io.exu_i0_br_index_r bp_ctl_ch.io.exu_i0_br_index_r := io.exu_i0_br_index_r
bp_ctl_ch.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb bp_ctl_ch.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb

18
src/main/scala/ifu/el2_ifu_aln_ctl.scala
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@ -42,7 +42,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W)) val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
val ifu_pmu_instr_aligned = Output(Bool()) val ifu_pmu_instr_aligned = Output(Bool())
val ifu_i0_cinst = Output(UInt(16.W)) val ifu_i0_cinst = Output(UInt(16.W))
val i0_brp = Valid(new el2_br_pkt_t) val i0_brp = Output(new el2_br_pkt_t)
}) })
io.ifu_i0_valid := 0.U io.ifu_i0_valid := 0.U
io.ifu_i0_icaf := 0.U io.ifu_i0_icaf := 0.U
@ -377,25 +377,25 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0)) io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
io.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1)) io.i0_brp.ret := (first2B & alignret(0)) | (first4B & alignret(1))
val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1)) val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
io.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1)) io.i0_brp.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
io.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)), io.i0_brp.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
(first2B & alignhist0(0)) | (first4B & alignhist0(1))) (first2B & alignhist0(0)) | (first4B & alignhist0(1)))
val i0_ends_f1 = first4B & alignfromf1 val i0_ends_f1 = first4B & alignfromf1
io.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset) io.i0_brp.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
io.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett) io.i0_brp.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
io.i0_brp.bits.br_start_error := (first4B & alignval(1) & alignbrend(0)) io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0))
io.i0_brp.bits.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0)) io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
io.i0_brp.bits.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B) io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B)
io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash) io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)

14
src/main/scala/ifu/el2_ifu_bp_ctl.scala
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@ -13,7 +13,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val ifc_fetch_addr_f = Input(UInt(31.W)) val ifc_fetch_addr_f = Input(UInt(31.W))
val ifc_fetch_req_f = Input(Bool()) // Fetch request generated by the IFC val ifc_fetch_req_f = Input(Bool()) // Fetch request generated by the IFC
// Decode packet containing information if its a brnach or not // Decode packet containing information if its a brnach or not
val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t)) val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t)
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Way from where the btb got a hit val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Way from where the btb got a hit
val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_lower_wb = Input(Bool())
@ -83,12 +83,12 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
// Its a commit or update packet // Its a commit or update packet
val dec_tlu_br0_v_wb = io.dec_tlu_br0_r_pkt.valid val dec_tlu_br0_v_wb = io.dec_tlu_br0_r_pkt.valid
val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.bits.hist val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.hist
val dec_tlu_br0_addr_wb = io.exu_i0_br_index_r val dec_tlu_br0_addr_wb = io.exu_i0_br_index_r
val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.bits.br_error val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.br_error
val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.bits.middle val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.middle
val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.bits.way val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.way
val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.bits.br_start_error val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.br_start_error
val exu_i0_br_fghr_wb = io.exu_i0_br_fghr_r val exu_i0_br_fghr_wb = io.exu_i0_br_fghr_r
dec_tlu_error_wb := dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb dec_tlu_error_wb := dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb
@ -281,7 +281,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val bht_bank1_rd_data_f =WireInit(UInt(2.W), 0.U) val bht_bank1_rd_data_f =WireInit(UInt(2.W), 0.U)
val bht_bank0_rd_data_f =WireInit(UInt(2.W), 0.U) val bht_bank0_rd_data_f =WireInit(UInt(2.W), 0.U)
val bht_bank0_rd_data_p1_f =WireInit(UInt(2.W), 0.U) val bht_bank0_rd_data_p1_f =WireInit(UInt(2.W), 0.U)
// Depending on pc make the virtual bank as commented above // Depending on pc make the virtual bank as commented above
val bht_vbank0_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->bht_bank0_rd_data_f, val bht_vbank0_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->bht_bank0_rd_data_f,
io.ifc_fetch_addr_f(0).asBool->bht_bank1_rd_data_f)) io.ifc_fetch_addr_f(0).asBool->bht_bank1_rd_data_f))

15
src/main/scala/include/el2_bundle.scala
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@ -36,6 +36,7 @@ object el2_inst_pkt_t extends Enumeration{
} }
class el2_load_cam_pkt_t extends Bundle { class el2_load_cam_pkt_t extends Bundle {
val valid = UInt(1.W)
val wb = UInt(1.W) val wb = UInt(1.W)
val tag = UInt(3.W) val tag = UInt(3.W)
val rd = UInt(5.W) val rd = UInt(5.W)
@ -48,6 +49,7 @@ class el2_rets_pkt_t extends Bundle {
} }
class el2_br_pkt_t extends Bundle { class el2_br_pkt_t extends Bundle {
val valid = UInt(1.W)
val toffset = UInt(12.W) val toffset = UInt(12.W)
val hist = UInt(2.W) val hist = UInt(2.W)
val br_error = UInt(1.W) val br_error = UInt(1.W)
@ -60,6 +62,7 @@ class el2_br_pkt_t extends Bundle {
class el2_br_tlu_pkt_t extends Bundle { class el2_br_tlu_pkt_t extends Bundle {
val valid = UInt(1.W)
val hist = UInt(2.W) val hist = UInt(2.W)
val br_error = UInt(1.W) val br_error = UInt(1.W)
val br_start_error = UInt(1.W) val br_start_error = UInt(1.W)
@ -74,6 +77,7 @@ class el2_predict_pkt_t extends Bundle {
val pc4 = UInt(1.W) val pc4 = UInt(1.W)
val hist = UInt(2.W) val hist = UInt(2.W)
val toffset = UInt(12.W) val toffset = UInt(12.W)
// val valid = UInt(1.W)
val br_error = UInt(1.W) val br_error = UInt(1.W)
val br_start_error = UInt(1.W) val br_start_error = UInt(1.W)
val prett = UInt(31.W) val prett = UInt(31.W)
@ -157,14 +161,16 @@ class el2_lsu_pkt_t extends Bundle {
val store_data_bypass_d = Bool() val store_data_bypass_d = Bool()
val load_ldst_bypass_d = Bool() val load_ldst_bypass_d = Bool()
val store_data_bypass_m = Bool() val store_data_bypass_m = Bool()
// val valid = Bool()
} }
class el2_lsu_error_pkt_t extends Bundle { class el2_lsu_error_pkt_t extends Bundle {
// val exc_valid = UInt(1.W)
val single_ecc_error = UInt(1.W) val single_ecc_error = UInt(1.W)
val inst_type = UInt(1.W) //0: Load, 1: Store val inst_type = UInt(1.W) //0: Load, 1: Store
val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault
val mscause = UInt(1.W) val mscause = UInt(4.W)
val addr = UInt(1.W) val addr = UInt(32.W)
} }
class el2_dec_pkt_t extends Bundle { class el2_dec_pkt_t extends Bundle {
@ -221,6 +227,7 @@ class el2_dec_pkt_t extends Bundle {
} }
class el2_mul_pkt_t extends Bundle { class el2_mul_pkt_t extends Bundle {
// val valid = UInt(1.W)
val rs1_sign = UInt(1.W) val rs1_sign = UInt(1.W)
val rs2_sign = UInt(1.W) val rs2_sign = UInt(1.W)
val low = UInt(1.W) val low = UInt(1.W)
@ -242,6 +249,7 @@ class el2_mul_pkt_t extends Bundle {
} }
class el2_div_pkt_t extends Bundle { class el2_div_pkt_t extends Bundle {
// val valid = UInt(1.W)
val unsign = UInt(1.W) val unsign = UInt(1.W)
val rem = UInt(1.W) val rem = UInt(1.W)
} }
@ -250,6 +258,7 @@ class el2_ccm_ext_in_pkt_t extends Bundle {
val TEST1 = UInt(1.W) val TEST1 = UInt(1.W)
val RME = UInt(1.W) val RME = UInt(1.W)
val RM = UInt(4.W) val RM = UInt(4.W)
val LS = UInt(1.W) val LS = UInt(1.W)
val DS = UInt(1.W) val DS = UInt(1.W)
val SD = UInt(1.W) val SD = UInt(1.W)
@ -297,7 +306,7 @@ class el2_ic_tag_ext_in_pkt_t extends Bundle {
class el2_trigger_pkt_t extends Bundle { class el2_trigger_pkt_t extends Bundle {
val select = UInt(1.W) val select = UInt(1.W)
val match_ = UInt(1.W) val match_pkt = UInt(1.W)
val store = UInt(1.W) val store = UInt(1.W)
val load = UInt(1.W) val load = UInt(1.W)
val execute = UInt(1.W) val execute = UInt(1.W)

2
src/main/scala/lsu/el2_lsu_trigger.scala
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@ -17,7 +17,7 @@ class el2_lsu_trigger extends Module with RequireAsyncReset with el2_lib {
val lsu_match_data = (0 until 4).map(i=>Mux1H(Seq(!io.trigger_pkt_any(i).select.asBool->io.lsu_addr_m, (io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).store).asBool->store_data_trigger_m))) val lsu_match_data = (0 until 4).map(i=>Mux1H(Seq(!io.trigger_pkt_any(i).select.asBool->io.lsu_addr_m, (io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).store).asBool->store_data_trigger_m)))
io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.bits.store)| io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.bits.store)|
(io.trigger_pkt_any(i).load & io.lsu_pkt_m.bits.load & !io.trigger_pkt_any(i).select) )& (io.trigger_pkt_any(i).load & io.lsu_pkt_m.bits.load & !io.trigger_pkt_any(i).select) )&
rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_.asBool())).reverse.reduce(Cat(_,_)) rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_pkt.asBool())).reverse.reduce(Cat(_,_))
} }

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