Reset dontTouch for script

This commit is contained in:
waleed-lm 2020-12-14 11:58:20 +05:00
parent 5510d4f1b9
commit a9c909f648
9 changed files with 1723 additions and 1718 deletions

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@ -66,6 +66,18 @@
"target":"dbg.gated_latch", "target":"dbg.gated_latch",
"resourceId":"/vsrc/gated_latch.v" "resourceId":"/vsrc/gated_latch.v"
}, },
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~dbg|dbg>rst_not"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~dbg|dbg>rst_temp"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~dbg|dbg>dbg_dm_rst_l"
},
{ {
"class":"firrtl.options.TargetDirAnnotation", "class":"firrtl.options.TargetDirAnnotation",
"directory":"." "directory":"."

1931
dbg.fir

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1456
dbg.v

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@ -1,3 +1 @@
/home/waleedbinehsan/Desktop/Quasar/gated_latch.v /home/waleedbinehsan/Desktop/Quasar/gated_latch.v
/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
/home/waleedbinehsan/Desktop/Quasar/mem.sv

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@ -96,30 +96,37 @@ class dbg extends Module with lib with RequireAsyncReset {
val sb_free_clken = io.dmi_reg_en | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override; val sb_free_clken = io.dmi_reg_en | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override;
val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc
val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc
val dbg_dm_rst_l = io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)
val dbg_dm_rst_l = (io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)).asAsyncReset()
dontTouch(dbg_dm_rst_l)
val rst_temp = (dbg_dm_rst_l.asBool() & reset.asBool()).asAsyncReset()
dontTouch(rst_temp)
val rst_not = (!dbg_dm_rst_l.asBool).asAsyncReset()
dontTouch(rst_not)
io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool() io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool()
val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle) val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle)
val sbcs_sbbusyerror_wren = (sbcs_wren & io.dmi_reg_wdata(22)) | ((sb_state =/= sb_state_t.sbidle) & io.dmi_reg_en & val sbcs_sbbusyerror_wren = (sbcs_wren & io.dmi_reg_wdata(22)) | ((sb_state =/= sb_state_t.sbidle) & io.dmi_reg_en &
((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U))) ((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U)))
val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt() val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt()
val temp_sbcs_22 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { val temp_sbcs_22 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren) RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren)
} // sbcs_sbbusyerror_reg } // sbcs_sbbusyerror_reg
val temp_sbcs_21 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { val temp_sbcs_21 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren) RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren)
} // sbcs_sbbusy_reg } // sbcs_sbbusy_reg
val temp_sbcs_20 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { val temp_sbcs_20 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren) RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren)
} // sbcs_sbreadonaddr_reg } // sbcs_sbreadonaddr_reg
val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren) RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren)
} // sbcs_misc_reg } // sbcs_misc_reg
val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) { val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, rst_not) {
RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren) RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren)
} // sbcs_error_reg } // sbcs_error_reg
sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W)) sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W))
@ -144,11 +151,11 @@ class dbg extends Module with lib with RequireAsyncReset {
val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata | val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata |
Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32) Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32)
val sbdata0_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { val sbdata0_reg = withReset(dbg_dm_rst_l) {
rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode) rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode)
} // dbg_sbdata0_reg } // dbg_sbdata0_reg
val sbdata1_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { val sbdata1_reg = withReset(dbg_dm_rst_l) {
rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode) rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode)
} // dbg_sbdata1_reg } // dbg_sbdata1_reg
@ -156,7 +163,7 @@ class dbg extends Module with lib with RequireAsyncReset {
val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1 val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1
val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata | val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata |
Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr)) Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr))
sbaddress0_reg := withReset((dbg_dm_rst_l).asAsyncReset()) { sbaddress0_reg := withReset(dbg_dm_rst_l) {
rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode) rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode)
} // dbg_sbaddress0_reg } // dbg_sbaddress0_reg
@ -164,7 +171,7 @@ class dbg extends Module with lib with RequireAsyncReset {
val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15) val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15)
val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U)
val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en
val dm_temp = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { val dm_temp = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable( RegEnable(
Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)), Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)),
0.U, dmcontrol_wren) 0.U, dmcontrol_wren)
@ -177,7 +184,7 @@ class dbg extends Module with lib with RequireAsyncReset {
val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0) val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0)
dmcontrol_reg := temp dmcontrol_reg := temp
val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(dmcontrol_wren, 0.U) RegNext(dmcontrol_wren, 0.U)
} // dmcontrol_wrenff } // dmcontrol_wrenff
@ -190,15 +197,15 @@ class dbg extends Module with lib with RequireAsyncReset {
val temp_rst = reset.asBool() val temp_rst = reset.asBool()
dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool() dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool()
dmstatus_running := ~(dmstatus_unavail | dmstatus_halted) dmstatus_running := ~(dmstatus_unavail | dmstatus_halted)
dmstatus_resumeack := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { dmstatus_resumeack := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren) RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren)
} // dmstatus_resumeack_reg } // dmstatus_resumeack_reg
dmstatus_halted := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { dmstatus_halted := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U) RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U)
} // dmstatus_halted_reg } // dmstatus_halted_reg
dmstatus_havereset := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { dmstatus_havereset := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(Mux(dmstatus_havereset_wren, true.B, dmstatus_havereset) & !dmstatus_havereset_rst, false.B) RegNext(Mux(dmstatus_havereset_wren, true.B, dmstatus_havereset) & !dmstatus_havereset_rst, false.B)
} // dmstatus_havereset_reg } // dmstatus_havereset_reg
@ -222,11 +229,11 @@ class dbg extends Module with lib with RequireAsyncReset {
(Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) | (Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) |
(Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8)) (Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8))
val abs_temp_12 = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { val abs_temp_12 = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren) RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren)
} // dmabstractcs_busy_reg } // dmabstractcs_busy_reg
val abs_temp_10_8 = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { val abs_temp_10_8 = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(abstractcs_error_din(2, 0), 0.U) RegNext(abstractcs_error_din(2, 0), 0.U)
} // dmabstractcs_error_reg } // dmabstractcs_error_reg
@ -234,7 +241,7 @@ class dbg extends Module with lib with RequireAsyncReset {
val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted) val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted)
val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0)) val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0))
val command_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { val command_reg = withReset(dbg_dm_rst_l) {
rvdffe(command_din, command_wren,clock,io.scan_mode) rvdffe(command_din, command_wren,clock,io.scan_mode)
} // dmcommand_reg } // dmcommand_reg
@ -243,13 +250,13 @@ class dbg extends Module with lib with RequireAsyncReset {
val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1
val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata
val data0_reg = withReset((dbg_dm_rst_l).asAsyncReset()) { val data0_reg = withReset(dbg_dm_rst_l) {
rvdffe(data0_din,data0_reg_wren,clock,io.scan_mode) rvdffe(data0_din,data0_reg_wren,clock,io.scan_mode)
} // dbg_data0_reg } // dbg_data0_reg
val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted)) val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted))
val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata
data1_reg := withReset((dbg_dm_rst_l).asAsyncReset()) { data1_reg := withReset(dbg_dm_rst_l) {
rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode) rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode)
} // dbg_data1_reg } // dbg_data1_reg
@ -312,12 +319,12 @@ class dbg extends Module with lib with RequireAsyncReset {
Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg | Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg |
Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg
dbg_state := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l & temp_rst).asAsyncReset()) { dbg_state := withClockAndReset(dbg_free_clk, rst_temp) {
RegEnable(dbg_nxtstate, 0.U, dbg_state_en) RegEnable(dbg_nxtstate, 0.U, dbg_state_en)
} // dbg_state_reg } // dbg_state_reg
io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) { io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en) RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en)
} // dmi_rddata_reg } // dmi_rddata_reg
@ -394,7 +401,7 @@ class dbg extends Module with lib with RequireAsyncReset {
sbaddress0_reg_wren1 := sbcs_reg(16) sbaddress0_reg_wren1 := sbcs_reg(16)
}} }}
sb_state := withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) { sb_state := withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(sb_nxtstate, 0.U, sb_state_en) RegEnable(sb_nxtstate, 0.U, sb_state_en)
} // sb_state_reg } // sb_state_reg
@ -450,3 +457,6 @@ class dbg extends Module with lib with RequireAsyncReset {
io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write
io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type
} }
object db_obj extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
}

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