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This commit is contained in:
​Laraib Khan 2021-01-25 17:58:38 +05:00
parent 208045e9c3
commit fd4ab0599d
137 changed files with 93213 additions and 1300 deletions
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160
exu.anno.json Normal file
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_exu_bp_exu_mp_fghr",
"sources":[
"~exu|exu>io_dec_exu_tlu_exu_dec_tlu_flush_lower_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_lsu_exu_exu_lsu_rs2_d",
"sources":[
"~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs2_d",
"~exu|exu>io_dec_qual_lsu_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs2_en_d",
"~exu|exu>io_lsu_exu_lsu_nonblock_load_data",
"~exu|exu>io_dec_exu_decode_exu_dec_extint_stall",
"~exu|exu>io_dec_exu_decode_exu_exu_i0_result_x",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_result_r",
"~exu|exu>io_lsu_exu_lsu_result_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_exu_flush_path_final",
"sources":[
"~exu|exu>io_dec_exu_tlu_exu_dec_tlu_flush_path_r",
"~exu|exu>io_dec_exu_tlu_exu_dec_tlu_flush_lower_r",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_jal",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_sub",
"~exu|exu>io_dec_exu_ib_exu_dec_i0_pc_d",
"~exu|exu>io_dec_exu_dec_alu_dec_i0_br_immed_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall",
"~exu|exu>io_dec_exu_dec_alu_dec_i0_alu_decode_d",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_predict_t",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_predict_nt",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_bge",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_blt",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_beq",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_bne",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_unsign",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett",
"~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs2_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_immed_d",
"~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs1_d",
"~exu|exu>io_dbg_cmd_wrdata",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs2_en_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d",
"~exu|exu>io_lsu_exu_lsu_nonblock_load_data",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_en_d",
"~exu|exu>io_dec_exu_decode_exu_exu_i0_result_x",
"~exu|exu>io_dec_exu_ib_exu_dec_debug_wdata_rs1_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_result_r",
"~exu|exu>io_lsu_exu_lsu_result_m",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_select_pc_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_exu_bp_exu_i0_br_index_r",
"sources":[
"~exu|exu>io_dec_exu_tlu_exu_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_lsu_exu_exu_lsu_rs1_d",
"sources":[
"~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs1_d",
"~exu|exu>io_dec_exu_tlu_exu_dec_tlu_meihap",
"~exu|exu>io_dec_exu_decode_exu_dec_extint_stall",
"~exu|exu>io_dec_qual_lsu_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_en_d",
"~exu|exu>io_lsu_exu_lsu_nonblock_load_data",
"~exu|exu>io_dec_exu_decode_exu_exu_i0_result_x",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_result_r",
"~exu|exu>io_lsu_exu_lsu_result_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_exu_flush_final",
"sources":[
"~exu|exu>io_dec_exu_tlu_exu_dec_tlu_flush_lower_r",
"~exu|exu>io_dec_exu_dec_alu_dec_i0_alu_decode_d",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_jal",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_predict_t",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_predict_nt",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_bge",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_sub",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_blt",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_beq",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_bne",
"~exu|exu>io_dec_exu_decode_exu_i0_ap_unsign",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall",
"~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs1_d",
"~exu|exu>io_dec_exu_gpr_exu_gpr_i0_rs2_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_immed_d",
"~exu|exu>io_dbg_cmd_wrdata",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_en_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs2_en_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d",
"~exu|exu>io_lsu_exu_lsu_nonblock_load_data",
"~exu|exu>io_dec_exu_ib_exu_dec_i0_pc_d",
"~exu|exu>io_dec_exu_ib_exu_dec_debug_wdata_rs1_d",
"~exu|exu>io_dec_exu_decode_exu_exu_i0_result_x",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_select_pc_d",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_result_r",
"~exu|exu>io_lsu_exu_lsu_result_m",
"~exu|exu>io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_exu_div_result",
"sources":[
"~exu|exu>io_dec_exu_dec_div_dec_div_cancel"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu|exu>io_exu_div_wren",
"sources":[
"~exu|exu>io_dec_exu_dec_div_dec_div_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~exu|exu>i0_rs2_d"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_valid",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_misp",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_flush_upper_x",
"~exu_alu_ctl|exu_alu_ctl>io_dec_tlu_flush_lower_r",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_predict_t",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_predict_nt",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_prett",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bge",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_blt",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_beq",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bne",
"~exu_alu_ctl|exu_alu_ctl>io_a_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_unsign",
"~exu_alu_ctl|exu_alu_ctl>io_b_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_toffset",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_toffset"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_flush_path_out",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub",
"~exu_alu_ctl|exu_alu_ctl>io_dec_i0_pc_d",
"~exu_alu_ctl|exu_alu_ctl>io_dec_alu_dec_i0_br_immed_d",
"~exu_alu_ctl|exu_alu_ctl>io_b_in",
"~exu_alu_ctl|exu_alu_ctl>io_a_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_pret",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_pred_correct_out",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_dec_alu_dec_i0_alu_decode_d",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_predict_nt",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_predict_t",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bge",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_blt",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_beq",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bne",
"~exu_alu_ctl|exu_alu_ctl>io_a_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_unsign",
"~exu_alu_ctl|exu_alu_ctl>io_b_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_pja",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_pc4",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pc4"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_ataken",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bge",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_blt",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_beq",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bne",
"~exu_alu_ctl|exu_alu_ctl>io_a_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_unsign",
"~exu_alu_ctl|exu_alu_ctl>io_b_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_way",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_way"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_pcall",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_hist",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_hist",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bge",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_blt",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_beq",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bne",
"~exu_alu_ctl|exu_alu_ctl>io_a_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_unsign",
"~exu_alu_ctl|exu_alu_ctl>io_b_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_br_start_error",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_br_start_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_br_error",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_br_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_prett",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_prett"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_flush_final_out",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_dec_tlu_flush_lower_r",
"~exu_alu_ctl|exu_alu_ctl>io_dec_alu_dec_i0_alu_decode_d",
"~exu_alu_ctl|exu_alu_ctl>io_flush_upper_x",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_prett",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_predict_t",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_predict_nt",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bge",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_blt",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_beq",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bne",
"~exu_alu_ctl|exu_alu_ctl>io_a_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_unsign",
"~exu_alu_ctl|exu_alu_ctl>io_b_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_boffset",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_boffset"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_flush_upper_out",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_dec_tlu_flush_lower_r",
"~exu_alu_ctl|exu_alu_ctl>io_dec_alu_dec_i0_alu_decode_d",
"~exu_alu_ctl|exu_alu_ctl>io_flush_upper_x",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_prett",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_predict_t",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_predict_nt",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bge",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_blt",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_beq",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bne",
"~exu_alu_ctl|exu_alu_ctl>io_a_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_unsign",
"~exu_alu_ctl|exu_alu_ctl>io_b_in"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_alu_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_alu_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1335
exu_alu_ctl.fir Normal file
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582
exu_alu_ctl.v Normal file
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@ -0,0 +1,582 @@
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module exu_alu_ctl(
input clock,
input reset,
input io_dec_alu_dec_i0_alu_decode_d,
input io_dec_alu_dec_csr_ren_d,
input [11:0] io_dec_alu_dec_i0_br_immed_d,
output [30:0] io_dec_alu_exu_i0_pc_x,
input [31:0] io_csr_rddata_in,
input [30:0] io_dec_i0_pc_d,
input io_scan_mode,
input io_flush_upper_x,
input io_dec_tlu_flush_lower_r,
input io_enable,
input io_i0_ap_clz,
input io_i0_ap_ctz,
input io_i0_ap_pcnt,
input io_i0_ap_sext_b,
input io_i0_ap_sext_h,
input io_i0_ap_slo,
input io_i0_ap_sro,
input io_i0_ap_min,
input io_i0_ap_max,
input io_i0_ap_pack,
input io_i0_ap_packu,
input io_i0_ap_packh,
input io_i0_ap_rol,
input io_i0_ap_ror,
input io_i0_ap_grev,
input io_i0_ap_gorc,
input io_i0_ap_zbb,
input io_i0_ap_sbset,
input io_i0_ap_sbclr,
input io_i0_ap_sbinv,
input io_i0_ap_sbext,
input io_i0_ap_sh1add,
input io_i0_ap_sh2add,
input io_i0_ap_sh3add,
input io_i0_ap_zba,
input io_i0_ap_land,
input io_i0_ap_lor,
input io_i0_ap_lxor,
input io_i0_ap_sll,
input io_i0_ap_srl,
input io_i0_ap_sra,
input io_i0_ap_beq,
input io_i0_ap_bne,
input io_i0_ap_blt,
input io_i0_ap_bge,
input io_i0_ap_add,
input io_i0_ap_sub,
input io_i0_ap_slt,
input io_i0_ap_unsign,
input io_i0_ap_jal,
input io_i0_ap_predict_t,
input io_i0_ap_predict_nt,
input io_i0_ap_csr_write,
input io_i0_ap_csr_imm,
input [31:0] io_a_in,
input [31:0] io_b_in,
input io_pp_in_valid,
input io_pp_in_bits_misp,
input io_pp_in_bits_ataken,
input io_pp_in_bits_boffset,
input io_pp_in_bits_pc4,
input [1:0] io_pp_in_bits_hist,
input [11:0] io_pp_in_bits_toffset,
input io_pp_in_bits_br_error,
input io_pp_in_bits_br_start_error,
input [30:0] io_pp_in_bits_prett,
input io_pp_in_bits_pcall,
input io_pp_in_bits_pret,
input io_pp_in_bits_pja,
input io_pp_in_bits_way,
output [31:0] io_result_ff,
output io_flush_upper_out,
output io_flush_final_out,
output [30:0] io_flush_path_out,
output io_pred_correct_out,
output io_predict_p_out_valid,
output io_predict_p_out_bits_misp,
output io_predict_p_out_bits_ataken,
output io_predict_p_out_bits_boffset,
output io_predict_p_out_bits_pc4,
output [1:0] io_predict_p_out_bits_hist,
output [11:0] io_predict_p_out_bits_toffset,
output io_predict_p_out_bits_br_error,
output io_predict_p_out_bits_br_start_error,
output [30:0] io_predict_p_out_bits_prett,
output io_predict_p_out_bits_pcall,
output io_predict_p_out_bits_pret,
output io_predict_p_out_bits_pja,
output io_predict_p_out_bits_way
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_io_en; // @[lib.scala 399:23]
wire _T_1 = io_b_in[4:0] == 5'h1f; // @[exu_alu_ctl.scala 87:55]
wire ap_rev = io_i0_ap_grev & _T_1; // @[exu_alu_ctl.scala 87:39]
wire _T_4 = io_b_in[4:0] == 5'h18; // @[exu_alu_ctl.scala 88:55]
wire ap_rev8 = io_i0_ap_grev & _T_4; // @[exu_alu_ctl.scala 88:39]
wire _T_7 = io_b_in[4:0] == 5'h7; // @[exu_alu_ctl.scala 89:55]
wire ap_orc_b = io_i0_ap_gorc & _T_7; // @[exu_alu_ctl.scala 89:39]
wire _T_10 = io_b_in[4:0] == 5'h10; // @[exu_alu_ctl.scala 90:55]
wire ap_orc16 = io_i0_ap_gorc & _T_10; // @[exu_alu_ctl.scala 90:39]
reg [30:0] _T_14; // @[Reg.scala 27:20]
wire _T_15 = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[exu_alu_ctl.scala 135:43]
reg [31:0] _T_18; // @[Reg.scala 27:20]
wire [31:0] _T_153 = io_csr_rddata_in; // @[Mux.scala 27:72]
wire [32:0] _T_151 = {{1{_T_153[31]}},_T_153}; // @[Mux.scala 27:72 Mux.scala 27:72]
wire [32:0] _T_172 = io_dec_alu_dec_csr_ren_d ? $signed(_T_151) : $signed(33'sh0); // @[Mux.scala 27:72]
wire _T_94 = ~io_i0_ap_zbb; // @[exu_alu_ctl.scala 160:22]
wire _T_95 = io_i0_ap_land & _T_94; // @[exu_alu_ctl.scala 160:20]
wire [32:0] _T_98 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
wire [32:0] _T_99 = {1'h0,io_a_in}; // @[exu_alu_ctl.scala 160:67]
wire [31:0] _T_100 = io_b_in; // @[exu_alu_ctl.scala 160:85]
wire [32:0] _GEN_2 = {{1{_T_100[31]}},_T_100}; // @[exu_alu_ctl.scala 160:74]
wire [32:0] _T_156 = $signed(_T_99) & $signed(_GEN_2); // @[Mux.scala 27:72]
wire [32:0] _T_173 = _T_95 ? $signed(_T_156) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] _T_180 = $signed(_T_172) | $signed(_T_173); // @[Mux.scala 27:72]
wire _T_104 = io_i0_ap_lor & _T_94; // @[exu_alu_ctl.scala 161:20]
wire [32:0] _T_159 = $signed(_T_99) | $signed(_GEN_2); // @[Mux.scala 27:72]
wire [32:0] _T_174 = _T_104 ? $signed(_T_159) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] _T_182 = $signed(_T_180) | $signed(_T_174); // @[Mux.scala 27:72]
wire _T_113 = io_i0_ap_lxor & _T_94; // @[exu_alu_ctl.scala 162:20]
wire [32:0] _T_162 = $signed(_T_99) ^ $signed(_GEN_2); // @[Mux.scala 27:72]
wire [32:0] _T_175 = _T_113 ? $signed(_T_162) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] _T_184 = $signed(_T_182) | $signed(_T_175); // @[Mux.scala 27:72]
wire _T_121 = io_i0_ap_land & io_i0_ap_zbb; // @[exu_alu_ctl.scala 163:20]
wire [31:0] _T_128 = ~io_b_in; // @[exu_alu_ctl.scala 163:76]
wire [32:0] _GEN_5 = {{1{_T_128[31]}},_T_128}; // @[exu_alu_ctl.scala 163:74]
wire [32:0] _T_165 = $signed(_T_99) & $signed(_GEN_5); // @[Mux.scala 27:72]
wire [32:0] _T_176 = _T_121 ? $signed(_T_165) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] _T_186 = $signed(_T_184) | $signed(_T_176); // @[Mux.scala 27:72]
wire _T_131 = io_i0_ap_lor & io_i0_ap_zbb; // @[exu_alu_ctl.scala 164:20]
wire [32:0] _T_168 = $signed(_T_99) | $signed(_GEN_5); // @[Mux.scala 27:72]
wire [32:0] _T_177 = _T_131 ? $signed(_T_168) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] _T_188 = $signed(_T_186) | $signed(_T_177); // @[Mux.scala 27:72]
wire _T_141 = io_i0_ap_lxor & io_i0_ap_zbb; // @[exu_alu_ctl.scala 165:20]
wire [32:0] _T_171 = $signed(_T_99) ^ $signed(_GEN_5); // @[Mux.scala 27:72]
wire [32:0] _T_178 = _T_141 ? $signed(_T_171) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] lout = $signed(_T_188) | $signed(_T_178); // @[Mux.scala 27:72]
wire _T_836 = io_i0_ap_sll | io_i0_ap_srl; // @[exu_alu_ctl.scala 293:44]
wire _T_837 = _T_836 | io_i0_ap_sra; // @[exu_alu_ctl.scala 293:59]
wire _T_840 = _T_837 | io_i0_ap_rol; // @[exu_alu_ctl.scala 293:92]
wire sel_shift = _T_840 | io_i0_ap_ror; // @[exu_alu_ctl.scala 293:101]
wire [31:0] _T_887 = sel_shift ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [30:0] _T_345 = io_a_in[31] ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
wire [30:0] _T_352 = io_i0_ap_sra ? _T_345 : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_353 = io_i0_ap_sll ? io_a_in[30:0] : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_358 = _T_352 | _T_353; // @[Mux.scala 27:72]
wire [30:0] _T_354 = io_i0_ap_rol ? io_a_in[30:0] : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_359 = _T_358 | _T_354; // @[Mux.scala 27:72]
wire [30:0] _T_355 = io_i0_ap_ror ? io_a_in[30:0] : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_360 = _T_359 | _T_355; // @[Mux.scala 27:72]
wire [62:0] shift_extend = {_T_360,io_a_in}; // @[Cat.scala 29:58]
wire [5:0] _T_195 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58]
wire [5:0] _T_197 = 6'h20 - _T_195; // @[exu_alu_ctl.scala 179:41]
wire [5:0] _T_218 = io_i0_ap_sll ? _T_197 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_219 = io_i0_ap_srl ? _T_195 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_226 = _T_218 | _T_219; // @[Mux.scala 27:72]
wire [5:0] _T_220 = io_i0_ap_sra ? _T_195 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_227 = _T_226 | _T_220; // @[Mux.scala 27:72]
wire [5:0] _T_221 = io_i0_ap_rol ? _T_197 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_228 = _T_227 | _T_221; // @[Mux.scala 27:72]
wire [5:0] _T_222 = io_i0_ap_ror ? _T_195 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_229 = _T_228 | _T_222; // @[Mux.scala 27:72]
wire [5:0] _T_225 = io_i0_ap_sbext ? _T_195 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] shift_amount = _T_229 | _T_225; // @[Mux.scala 27:72]
wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[exu_alu_ctl.scala 202:32]
wire [4:0] _T_238 = {io_i0_ap_sll,io_i0_ap_sll,io_i0_ap_sll,io_i0_ap_sll,io_i0_ap_sll}; // @[Cat.scala 29:58]
wire [4:0] _T_240 = _T_238 & io_b_in[4:0]; // @[exu_alu_ctl.scala 189:73]
wire [62:0] _T_241 = 63'hffffffff << _T_240; // @[exu_alu_ctl.scala 189:39]
wire [31:0] shift_mask = _T_241[31:0]; // @[exu_alu_ctl.scala 189:14]
wire [31:0] sout = shift_long[31:0] & shift_mask; // @[exu_alu_ctl.scala 204:34]
wire [31:0] _T_889 = _T_887 & sout; // @[exu_alu_ctl.scala 304:56]
wire [31:0] _T_890 = lout[31:0] | _T_889; // @[exu_alu_ctl.scala 304:31]
wire _T_841 = io_i0_ap_add | io_i0_ap_sub; // @[exu_alu_ctl.scala 294:44]
wire _T_843 = ~io_i0_ap_slt; // @[exu_alu_ctl.scala 294:71]
wire _T_844 = _T_841 & _T_843; // @[exu_alu_ctl.scala 294:69]
wire _T_845 = ~io_i0_ap_min; // @[exu_alu_ctl.scala 294:87]
wire _T_846 = _T_844 & _T_845; // @[exu_alu_ctl.scala 294:85]
wire _T_847 = ~io_i0_ap_max; // @[exu_alu_ctl.scala 294:97]
wire sel_adder = _T_846 & _T_847; // @[exu_alu_ctl.scala 294:95]
wire [31:0] _T_892 = sel_adder ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [32:0] _T_57 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
wire [31:0] _T_58 = ~io_b_in; // @[exu_alu_ctl.scala 146:74]
wire [32:0] _T_59 = {1'h0,_T_58}; // @[Cat.scala 29:58]
wire [32:0] _T_61 = _T_57 + _T_59; // @[exu_alu_ctl.scala 146:59]
wire [32:0] _T_62 = {32'h0,io_i0_ap_sub}; // @[Cat.scala 29:58]
wire [32:0] _T_64 = _T_61 + _T_62; // @[exu_alu_ctl.scala 146:84]
wire [32:0] _T_67 = {1'h0,io_b_in}; // @[Cat.scala 29:58]
wire [32:0] _T_69 = _T_98 + _T_67; // @[exu_alu_ctl.scala 146:139]
wire [32:0] _T_72 = _T_69 + _T_62; // @[exu_alu_ctl.scala 146:164]
wire [32:0] aout = io_i0_ap_sub ? _T_64 : _T_72; // @[exu_alu_ctl.scala 146:14]
wire [31:0] _T_894 = _T_892 & aout[31:0]; // @[exu_alu_ctl.scala 305:28]
wire [31:0] _T_895 = _T_890 | _T_894; // @[exu_alu_ctl.scala 304:71]
wire _T_848 = io_i0_ap_jal | io_pp_in_bits_pcall; // @[exu_alu_ctl.scala 295:44]
wire _T_849 = _T_848 | io_pp_in_bits_pja; // @[exu_alu_ctl.scala 295:66]
wire sel_pc = _T_849 | io_pp_in_bits_pret; // @[exu_alu_ctl.scala 295:86]
wire [31:0] _T_897 = sel_pc ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [12:0] _T_853 = {io_dec_alu_dec_i0_br_immed_d,1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_852 = {io_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_856 = _T_852[12:1] + _T_853[12:1]; // @[lib.scala 68:31]
wire _T_865 = ~_T_856[12]; // @[lib.scala 72:28]
wire _T_866 = _T_853[12] ^ _T_865; // @[lib.scala 72:26]
wire [18:0] _T_877 = _T_866 ? _T_852[31:13] : 19'h0; // @[Mux.scala 27:72]
wire _T_869 = ~_T_853[12]; // @[lib.scala 73:20]
wire _T_871 = _T_869 & _T_856[12]; // @[lib.scala 73:26]
wire [18:0] _T_859 = _T_852[31:13] + 19'h1; // @[lib.scala 69:27]
wire [18:0] _T_878 = _T_871 ? _T_859 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_880 = _T_877 | _T_878; // @[Mux.scala 27:72]
wire _T_875 = _T_853[12] & _T_865; // @[lib.scala 74:26]
wire [18:0] _T_862 = _T_852[31:13] - 19'h1; // @[lib.scala 70:27]
wire [18:0] _T_879 = _T_875 ? _T_862 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_881 = _T_880 | _T_879; // @[Mux.scala 27:72]
wire [31:0] pcout = {_T_881,_T_856[11:0],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_898 = _T_897 & pcout; // @[exu_alu_ctl.scala 306:28]
wire [31:0] _T_899 = _T_895 | _T_898; // @[exu_alu_ctl.scala 305:43]
wire [31:0] _T_901 = io_i0_ap_csr_write ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_902 = io_i0_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[exu_alu_ctl.scala 307:51]
wire [31:0] _T_903 = _T_901 & _T_902; // @[exu_alu_ctl.scala 307:34]
wire [31:0] _T_904 = _T_899 | _T_903; // @[exu_alu_ctl.scala 306:41]
wire _T_88 = ~io_i0_ap_unsign; // @[exu_alu_ctl.scala 154:30]
wire neg = aout[31]; // @[exu_alu_ctl.scala 153:34]
wire _T_75 = ~io_a_in[31]; // @[exu_alu_ctl.scala 149:14]
wire [31:0] bm = io_i0_ap_sub ? _T_58 : io_b_in; // @[exu_alu_ctl.scala 143:17]
wire _T_77 = ~bm[31]; // @[exu_alu_ctl.scala 149:29]
wire _T_78 = _T_75 & _T_77; // @[exu_alu_ctl.scala 149:27]
wire _T_80 = _T_78 & neg; // @[exu_alu_ctl.scala 149:37]
wire _T_83 = io_a_in[31] & bm[31]; // @[exu_alu_ctl.scala 149:66]
wire _T_85 = ~neg; // @[exu_alu_ctl.scala 149:78]
wire _T_86 = _T_83 & _T_85; // @[exu_alu_ctl.scala 149:76]
wire ov = _T_80 | _T_86; // @[exu_alu_ctl.scala 149:50]
wire _T_89 = neg ^ ov; // @[exu_alu_ctl.scala 154:54]
wire _T_90 = _T_88 & _T_89; // @[exu_alu_ctl.scala 154:47]
wire cout = aout[32]; // @[exu_alu_ctl.scala 147:18]
wire _T_91 = ~cout; // @[exu_alu_ctl.scala 154:84]
wire _T_92 = io_i0_ap_unsign & _T_91; // @[exu_alu_ctl.scala 154:82]
wire lt = _T_90 | _T_92; // @[exu_alu_ctl.scala 154:61]
wire slt_one = io_i0_ap_slt & lt; // @[exu_alu_ctl.scala 298:43]
wire [31:0] _T_905 = {31'h0,slt_one}; // @[Cat.scala 29:58]
wire [31:0] _T_906 = _T_904 | _T_905; // @[exu_alu_ctl.scala 307:59]
wire [31:0] _T_908 = io_i0_ap_sbext ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_910 = {31'h0,sout[0]}; // @[Cat.scala 29:58]
wire [31:0] _T_911 = _T_908 & _T_910; // @[exu_alu_ctl.scala 309:28]
wire [31:0] _T_912 = _T_906 | _T_911; // @[exu_alu_ctl.scala 308:56]
wire _T_547 = io_i0_ap_clz | io_i0_ap_ctz; // @[exu_alu_ctl.scala 221:52]
wire [5:0] _T_549 = _T_547 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_445 = io_i0_ap_clz ? $signed(io_a_in) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [9:0] _T_416 = {io_a_in[0],io_a_in[1],io_a_in[2],io_a_in[3],io_a_in[4],io_a_in[5],io_a_in[6],io_a_in[7],io_a_in[8],io_a_in[9]}; // @[Cat.scala 29:58]
wire [18:0] _T_425 = {_T_416,io_a_in[10],io_a_in[11],io_a_in[12],io_a_in[13],io_a_in[14],io_a_in[15],io_a_in[16],io_a_in[17],io_a_in[18]}; // @[Cat.scala 29:58]
wire [27:0] _T_434 = {_T_425,io_a_in[19],io_a_in[20],io_a_in[21],io_a_in[22],io_a_in[23],io_a_in[24],io_a_in[25],io_a_in[26],io_a_in[27]}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_a_reverse_ff = {_T_434,io_a_in[28],io_a_in[29],io_a_in[30],io_a_in[31]}; // @[Cat.scala 29:58]
wire [31:0] _T_444 = {_T_434,io_a_in[28],io_a_in[29],io_a_in[30],io_a_in[31]}; // @[Mux.scala 27:72]
wire [31:0] _T_446 = io_i0_ap_ctz ? $signed(_T_444) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] bitmanip_lzd_in = $signed(_T_445) | $signed(_T_446); // @[Mux.scala 27:72]
wire [31:0] _T_451 = $signed(_T_445) | $signed(_T_446); // @[exu_alu_ctl.scala 219:75]
wire _T_452 = _T_451 == 32'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_454 = bitmanip_lzd_in[31:1] == 31'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_456 = bitmanip_lzd_in[31:2] == 30'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_458 = bitmanip_lzd_in[31:3] == 29'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_460 = bitmanip_lzd_in[31:4] == 28'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_462 = bitmanip_lzd_in[31:5] == 27'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_464 = bitmanip_lzd_in[31:6] == 26'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_466 = bitmanip_lzd_in[31:7] == 25'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_468 = bitmanip_lzd_in[31:8] == 24'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_470 = bitmanip_lzd_in[31:9] == 23'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_472 = bitmanip_lzd_in[31:10] == 22'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_474 = bitmanip_lzd_in[31:11] == 21'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_476 = bitmanip_lzd_in[31:12] == 20'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_478 = bitmanip_lzd_in[31:13] == 19'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_480 = bitmanip_lzd_in[31:14] == 18'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_482 = bitmanip_lzd_in[31:15] == 17'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_484 = bitmanip_lzd_in[31:16] == 16'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_486 = bitmanip_lzd_in[31:17] == 15'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_488 = bitmanip_lzd_in[31:18] == 14'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_490 = bitmanip_lzd_in[31:19] == 13'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_492 = bitmanip_lzd_in[31:20] == 12'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_494 = bitmanip_lzd_in[31:21] == 11'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_496 = bitmanip_lzd_in[31:22] == 10'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_498 = bitmanip_lzd_in[31:23] == 9'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_500 = bitmanip_lzd_in[31:24] == 8'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_502 = bitmanip_lzd_in[31:25] == 7'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_504 = bitmanip_lzd_in[31:26] == 6'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_506 = bitmanip_lzd_in[31:27] == 5'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_508 = bitmanip_lzd_in[31:28] == 4'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_510 = bitmanip_lzd_in[31:29] == 3'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_512 = bitmanip_lzd_in[31:30] == 2'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_514 = ~bitmanip_lzd_in[31]; // @[exu_alu_ctl.scala 219:81]
wire [1:0] _T_516 = _T_512 ? 2'h2 : {{1'd0}, _T_514}; // @[Mux.scala 98:16]
wire [1:0] _T_517 = _T_510 ? 2'h3 : _T_516; // @[Mux.scala 98:16]
wire [2:0] _T_518 = _T_508 ? 3'h4 : {{1'd0}, _T_517}; // @[Mux.scala 98:16]
wire [2:0] _T_519 = _T_506 ? 3'h5 : _T_518; // @[Mux.scala 98:16]
wire [2:0] _T_520 = _T_504 ? 3'h6 : _T_519; // @[Mux.scala 98:16]
wire [2:0] _T_521 = _T_502 ? 3'h7 : _T_520; // @[Mux.scala 98:16]
wire [3:0] _T_522 = _T_500 ? 4'h8 : {{1'd0}, _T_521}; // @[Mux.scala 98:16]
wire [3:0] _T_523 = _T_498 ? 4'h9 : _T_522; // @[Mux.scala 98:16]
wire [3:0] _T_524 = _T_496 ? 4'ha : _T_523; // @[Mux.scala 98:16]
wire [3:0] _T_525 = _T_494 ? 4'hb : _T_524; // @[Mux.scala 98:16]
wire [3:0] _T_526 = _T_492 ? 4'hc : _T_525; // @[Mux.scala 98:16]
wire [3:0] _T_527 = _T_490 ? 4'hd : _T_526; // @[Mux.scala 98:16]
wire [3:0] _T_528 = _T_488 ? 4'he : _T_527; // @[Mux.scala 98:16]
wire [3:0] _T_529 = _T_486 ? 4'hf : _T_528; // @[Mux.scala 98:16]
wire [4:0] _T_530 = _T_484 ? 5'h10 : {{1'd0}, _T_529}; // @[Mux.scala 98:16]
wire [4:0] _T_531 = _T_482 ? 5'h11 : _T_530; // @[Mux.scala 98:16]
wire [4:0] _T_532 = _T_480 ? 5'h12 : _T_531; // @[Mux.scala 98:16]
wire [4:0] _T_533 = _T_478 ? 5'h13 : _T_532; // @[Mux.scala 98:16]
wire [4:0] _T_534 = _T_476 ? 5'h14 : _T_533; // @[Mux.scala 98:16]
wire [4:0] _T_535 = _T_474 ? 5'h15 : _T_534; // @[Mux.scala 98:16]
wire [4:0] _T_536 = _T_472 ? 5'h16 : _T_535; // @[Mux.scala 98:16]
wire [4:0] _T_537 = _T_470 ? 5'h17 : _T_536; // @[Mux.scala 98:16]
wire [4:0] _T_538 = _T_468 ? 5'h18 : _T_537; // @[Mux.scala 98:16]
wire [4:0] _T_539 = _T_466 ? 5'h19 : _T_538; // @[Mux.scala 98:16]
wire [4:0] _T_540 = _T_464 ? 5'h1a : _T_539; // @[Mux.scala 98:16]
wire [4:0] _T_541 = _T_462 ? 5'h1b : _T_540; // @[Mux.scala 98:16]
wire [4:0] _T_542 = _T_460 ? 5'h1c : _T_541; // @[Mux.scala 98:16]
wire [4:0] _T_543 = _T_458 ? 5'h1d : _T_542; // @[Mux.scala 98:16]
wire [4:0] _T_544 = _T_456 ? 5'h1e : _T_543; // @[Mux.scala 98:16]
wire [4:0] _T_545 = _T_454 ? 5'h1f : _T_544; // @[Mux.scala 98:16]
wire [5:0] bitmanip_dw_lzd_enc = _T_452 ? 6'h20 : {{1'd0}, _T_545}; // @[Mux.scala 98:16]
wire [5:0] _GEN_8 = {{5'd0}, bitmanip_dw_lzd_enc[5]}; // @[exu_alu_ctl.scala 221:62]
wire [5:0] _T_551 = _T_549 & _GEN_8; // @[exu_alu_ctl.scala 221:62]
wire _T_553 = ~bitmanip_dw_lzd_enc[5]; // @[exu_alu_ctl.scala 221:96]
wire [4:0] _T_555 = _T_553 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
wire [4:0] _T_557 = _T_555 & bitmanip_dw_lzd_enc[4:0]; // @[exu_alu_ctl.scala 221:121]
wire [10:0] bitmanip_clz_ctz_result = {_T_551,_T_557}; // @[Cat.scala 29:58]
wire [31:0] _T_914 = {26'h0,bitmanip_clz_ctz_result[5:0]}; // @[Cat.scala 29:58]
wire [31:0] _T_915 = _T_912 | _T_914; // @[exu_alu_ctl.scala 309:56]
wire [5:0] _T_559 = io_i0_ap_pcnt ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_592 = io_a_in[0] + io_a_in[1]; // @[Bitwise.scala 47:55]
wire [1:0] _T_594 = io_a_in[2] + io_a_in[3]; // @[Bitwise.scala 47:55]
wire [2:0] _T_596 = _T_592 + _T_594; // @[Bitwise.scala 47:55]
wire [1:0] _T_598 = io_a_in[4] + io_a_in[5]; // @[Bitwise.scala 47:55]
wire [1:0] _T_600 = io_a_in[6] + io_a_in[7]; // @[Bitwise.scala 47:55]
wire [2:0] _T_602 = _T_598 + _T_600; // @[Bitwise.scala 47:55]
wire [3:0] _T_604 = _T_596 + _T_602; // @[Bitwise.scala 47:55]
wire [1:0] _T_606 = io_a_in[8] + io_a_in[9]; // @[Bitwise.scala 47:55]
wire [1:0] _T_608 = io_a_in[10] + io_a_in[11]; // @[Bitwise.scala 47:55]
wire [2:0] _T_610 = _T_606 + _T_608; // @[Bitwise.scala 47:55]
wire [1:0] _T_612 = io_a_in[12] + io_a_in[13]; // @[Bitwise.scala 47:55]
wire [1:0] _T_614 = io_a_in[14] + io_a_in[15]; // @[Bitwise.scala 47:55]
wire [2:0] _T_616 = _T_612 + _T_614; // @[Bitwise.scala 47:55]
wire [3:0] _T_618 = _T_610 + _T_616; // @[Bitwise.scala 47:55]
wire [4:0] _T_620 = _T_604 + _T_618; // @[Bitwise.scala 47:55]
wire [1:0] _T_622 = io_a_in[16] + io_a_in[17]; // @[Bitwise.scala 47:55]
wire [1:0] _T_624 = io_a_in[18] + io_a_in[19]; // @[Bitwise.scala 47:55]
wire [2:0] _T_626 = _T_622 + _T_624; // @[Bitwise.scala 47:55]
wire [1:0] _T_628 = io_a_in[20] + io_a_in[21]; // @[Bitwise.scala 47:55]
wire [1:0] _T_630 = io_a_in[22] + io_a_in[23]; // @[Bitwise.scala 47:55]
wire [2:0] _T_632 = _T_628 + _T_630; // @[Bitwise.scala 47:55]
wire [3:0] _T_634 = _T_626 + _T_632; // @[Bitwise.scala 47:55]
wire [1:0] _T_636 = io_a_in[24] + io_a_in[25]; // @[Bitwise.scala 47:55]
wire [1:0] _T_638 = io_a_in[26] + io_a_in[27]; // @[Bitwise.scala 47:55]
wire [2:0] _T_640 = _T_636 + _T_638; // @[Bitwise.scala 47:55]
wire [1:0] _T_642 = io_a_in[28] + io_a_in[29]; // @[Bitwise.scala 47:55]
wire [1:0] _T_644 = io_a_in[30] + io_a_in[31]; // @[Bitwise.scala 47:55]
wire [2:0] _T_646 = _T_642 + _T_644; // @[Bitwise.scala 47:55]
wire [3:0] _T_648 = _T_640 + _T_646; // @[Bitwise.scala 47:55]
wire [4:0] _T_650 = _T_634 + _T_648; // @[Bitwise.scala 47:55]
wire [5:0] _T_652 = _T_620 + _T_650; // @[Bitwise.scala 47:55]
wire [5:0] bitmanip_pcnt_result = _T_559 & _T_652; // @[exu_alu_ctl.scala 224:50]
wire [31:0] _T_917 = {26'h0,bitmanip_pcnt_result}; // @[Cat.scala 29:58]
wire [31:0] _T_918 = _T_915 | _T_917; // @[exu_alu_ctl.scala 310:52]
wire [23:0] _T_656 = io_a_in[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_658 = {_T_656,io_a_in[7:0]}; // @[Cat.scala 29:58]
wire [31:0] _T_664 = io_i0_ap_sext_b ? _T_658 : 32'h0; // @[Mux.scala 27:72]
wire [15:0] _T_661 = io_a_in[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_663 = {_T_661,io_a_in[15:0]}; // @[Cat.scala 29:58]
wire [31:0] _T_665 = io_i0_ap_sext_h ? _T_663 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] bitmanip_sext_result = _T_664 | _T_665; // @[Mux.scala 27:72]
wire [31:0] _T_920 = _T_918 | bitmanip_sext_result; // @[exu_alu_ctl.scala 311:52]
wire bitmanip_minmax_sel = io_i0_ap_min | io_i0_ap_max; // @[exu_alu_ctl.scala 233:46]
wire ge = ~lt; // @[exu_alu_ctl.scala 155:29]
wire bitmanip_minmax_sel_a = ge ^ io_i0_ap_min; // @[exu_alu_ctl.scala 235:43]
wire _T_667 = bitmanip_minmax_sel & bitmanip_minmax_sel_a; // @[exu_alu_ctl.scala 238:26]
wire [31:0] _T_677 = _T_667 ? $signed(io_a_in) : $signed(32'sh0); // @[Mux.scala 27:72]
wire _T_668 = ~bitmanip_minmax_sel_a; // @[exu_alu_ctl.scala 239:28]
wire _T_669 = bitmanip_minmax_sel & _T_668; // @[exu_alu_ctl.scala 239:26]
wire [31:0] _T_678 = _T_669 ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_921 = $signed(_T_677) | $signed(_T_678); // @[exu_alu_ctl.scala 313:27]
wire [31:0] _T_922 = _T_920 | _T_921; // @[exu_alu_ctl.scala 312:35]
wire [31:0] _T_684 = io_i0_ap_pack ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_687 = {io_b_in[15:0],io_a_in[15:0]}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_pack_result = _T_684 & _T_687; // @[exu_alu_ctl.scala 244:50]
wire [31:0] _T_924 = _T_922 | bitmanip_pack_result; // @[exu_alu_ctl.scala 313:35]
wire [31:0] _T_689 = io_i0_ap_packu ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_692 = {io_b_in[31:16],io_a_in[31:16]}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_packu_result = _T_689 & _T_692; // @[exu_alu_ctl.scala 245:50]
wire [31:0] _T_926 = _T_924 | bitmanip_packu_result; // @[exu_alu_ctl.scala 314:35]
wire [31:0] _T_694 = io_i0_ap_packh ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_698 = {16'h0,io_b_in[7:0],io_a_in[7:0]}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_packh_result = _T_694 & _T_698; // @[exu_alu_ctl.scala 246:50]
wire [31:0] _T_928 = _T_926 | bitmanip_packh_result; // @[exu_alu_ctl.scala 315:35]
wire [31:0] _T_700 = ap_rev ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] bitmanip_rev_result = _T_700 & bitmanip_a_reverse_ff; // @[exu_alu_ctl.scala 252:48]
wire [31:0] _T_930 = _T_928 | bitmanip_rev_result; // @[exu_alu_ctl.scala 316:35]
wire [31:0] _T_765 = ap_rev8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_772 = {io_a_in[7:0],io_a_in[15:8],io_a_in[23:16],io_a_in[31:24]}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_rev8_result = _T_765 & _T_772; // @[exu_alu_ctl.scala 254:50]
wire [31:0] _T_932 = _T_930 | bitmanip_rev8_result; // @[exu_alu_ctl.scala 317:35]
wire [31:0] _T_774 = ap_orc_b ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire _T_788 = |io_a_in[31:24]; // @[exu_alu_ctl.scala 279:117]
wire [7:0] _T_790 = _T_788 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire _T_784 = |io_a_in[23:16]; // @[exu_alu_ctl.scala 279:117]
wire [7:0] _T_786 = _T_784 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire _T_780 = |io_a_in[15:8]; // @[exu_alu_ctl.scala 279:117]
wire [7:0] _T_782 = _T_780 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire _T_776 = |io_a_in[7:0]; // @[exu_alu_ctl.scala 279:117]
wire [7:0] _T_778 = _T_776 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_793 = {_T_790,_T_786,_T_782,_T_778}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_orc_b_result = _T_774 & _T_793; // @[exu_alu_ctl.scala 279:50]
wire [31:0] _T_934 = _T_932 | bitmanip_orc_b_result; // @[exu_alu_ctl.scala 318:35]
wire [31:0] _T_795 = ap_orc16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [15:0] _T_798 = io_a_in[31:16] | io_a_in[15:0]; // @[exu_alu_ctl.scala 281:71]
wire [31:0] _T_802 = {_T_798,_T_798}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_orc16_result = _T_795 & _T_802; // @[exu_alu_ctl.scala 281:50]
wire [31:0] _T_936 = _T_934 | bitmanip_orc16_result; // @[exu_alu_ctl.scala 319:35]
wire [62:0] bitmanip_sb_1hot = 63'h1 << io_b_in[4:0]; // @[exu_alu_ctl.scala 285:53]
wire [31:0] _T_805 = bitmanip_sb_1hot[31:0]; // @[exu_alu_ctl.scala 288:53]
wire [31:0] _T_820 = $signed(io_a_in) | $signed(_T_805); // @[Mux.scala 27:72]
wire [31:0] _T_827 = io_i0_ap_sbset ? $signed(_T_820) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_811 = ~_T_805; // @[exu_alu_ctl.scala 289:29]
wire [31:0] _T_823 = $signed(io_a_in) & $signed(_T_811); // @[Mux.scala 27:72]
wire [31:0] _T_828 = io_i0_ap_sbclr ? $signed(_T_823) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_831 = $signed(_T_827) | $signed(_T_828); // @[Mux.scala 27:72]
wire [31:0] _T_826 = $signed(io_a_in) ^ $signed(_T_805); // @[Mux.scala 27:72]
wire [31:0] _T_829 = io_i0_ap_sbinv ? $signed(_T_826) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_937 = $signed(_T_831) | $signed(_T_829); // @[exu_alu_ctl.scala 321:21]
wire [31:0] result = _T_936 | _T_937; // @[exu_alu_ctl.scala 320:35]
wire eq = $signed(io_a_in) == $signed(io_b_in); // @[exu_alu_ctl.scala 151:38]
wire ne = ~eq; // @[exu_alu_ctl.scala 152:29]
wire _T_941 = io_i0_ap_beq & eq; // @[exu_alu_ctl.scala 335:43]
wire _T_942 = io_i0_ap_bne & ne; // @[exu_alu_ctl.scala 335:65]
wire _T_943 = _T_941 | _T_942; // @[exu_alu_ctl.scala 335:49]
wire _T_944 = io_i0_ap_blt & lt; // @[exu_alu_ctl.scala 335:94]
wire _T_945 = _T_943 | _T_944; // @[exu_alu_ctl.scala 335:78]
wire _T_946 = io_i0_ap_bge & ge; // @[exu_alu_ctl.scala 335:116]
wire _T_947 = _T_945 | _T_946; // @[exu_alu_ctl.scala 335:100]
wire actual_taken = _T_947 | sel_pc; // @[exu_alu_ctl.scala 335:122]
wire _T_948 = io_dec_alu_dec_i0_alu_decode_d & io_i0_ap_predict_nt; // @[exu_alu_ctl.scala 340:61]
wire _T_949 = ~actual_taken; // @[exu_alu_ctl.scala 340:85]
wire _T_950 = _T_948 & _T_949; // @[exu_alu_ctl.scala 340:83]
wire _T_951 = ~sel_pc; // @[exu_alu_ctl.scala 340:101]
wire _T_952 = _T_950 & _T_951; // @[exu_alu_ctl.scala 340:99]
wire _T_953 = io_dec_alu_dec_i0_alu_decode_d & io_i0_ap_predict_t; // @[exu_alu_ctl.scala 340:145]
wire _T_954 = _T_953 & actual_taken; // @[exu_alu_ctl.scala 340:167]
wire _T_956 = _T_954 & _T_951; // @[exu_alu_ctl.scala 340:183]
wire _T_963 = io_i0_ap_predict_t & _T_949; // @[exu_alu_ctl.scala 345:48]
wire _T_964 = io_i0_ap_predict_nt & actual_taken; // @[exu_alu_ctl.scala 345:88]
wire cond_mispredict = _T_963 | _T_964; // @[exu_alu_ctl.scala 345:65]
wire _T_966 = io_pp_in_bits_prett != aout[31:1]; // @[exu_alu_ctl.scala 348:72]
wire target_mispredict = io_pp_in_bits_pret & _T_966; // @[exu_alu_ctl.scala 348:49]
wire _T_967 = io_i0_ap_jal | cond_mispredict; // @[exu_alu_ctl.scala 350:45]
wire _T_968 = _T_967 | target_mispredict; // @[exu_alu_ctl.scala 350:63]
wire _T_969 = _T_968 & io_dec_alu_dec_i0_alu_decode_d; // @[exu_alu_ctl.scala 350:84]
wire _T_970 = ~io_flush_upper_x; // @[exu_alu_ctl.scala 350:119]
wire _T_971 = _T_969 & _T_970; // @[exu_alu_ctl.scala 350:117]
wire _T_972 = ~io_dec_tlu_flush_lower_r; // @[exu_alu_ctl.scala 350:141]
wire _T_982 = io_pp_in_bits_hist[1] & io_pp_in_bits_hist[0]; // @[exu_alu_ctl.scala 355:44]
wire _T_984 = ~io_pp_in_bits_hist[0]; // @[exu_alu_ctl.scala 355:73]
wire _T_985 = _T_984 & actual_taken; // @[exu_alu_ctl.scala 355:96]
wire _T_986 = _T_982 | _T_985; // @[exu_alu_ctl.scala 355:70]
wire _T_988 = ~io_pp_in_bits_hist[1]; // @[exu_alu_ctl.scala 356:6]
wire _T_990 = _T_988 & _T_949; // @[exu_alu_ctl.scala 356:29]
wire _T_992 = io_pp_in_bits_hist[1] & actual_taken; // @[exu_alu_ctl.scala 356:72]
wire _T_993 = _T_990 | _T_992; // @[exu_alu_ctl.scala 356:47]
wire _T_997 = _T_970 & _T_972; // @[exu_alu_ctl.scala 359:56]
wire _T_998 = cond_mispredict | target_mispredict; // @[exu_alu_ctl.scala 359:103]
rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
assign io_dec_alu_exu_i0_pc_x = _T_14; // @[exu_alu_ctl.scala 133:26]
assign io_result_ff = _T_18; // @[exu_alu_ctl.scala 135:16]
assign io_flush_upper_out = _T_971 & _T_972; // @[exu_alu_ctl.scala 350:26]
assign io_flush_final_out = _T_971 | io_dec_tlu_flush_lower_r; // @[exu_alu_ctl.scala 351:26]
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[exu_alu_ctl.scala 342:22]
assign io_pred_correct_out = _T_952 | _T_956; // @[exu_alu_ctl.scala 340:26]
assign io_predict_p_out_valid = io_pp_in_valid; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_misp = _T_997 & _T_998; // @[exu_alu_ctl.scala 358:30 exu_alu_ctl.scala 359:35]
assign io_predict_p_out_bits_ataken = _T_947 | sel_pc; // @[exu_alu_ctl.scala 358:30 exu_alu_ctl.scala 360:35]
assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_hist = {_T_986,_T_993}; // @[exu_alu_ctl.scala 358:30 exu_alu_ctl.scala 361:35]
assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_br_error = io_pp_in_bits_br_error; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_br_start_error = io_pp_in_bits_br_start_error; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_prett = io_pp_in_bits_prett; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_pcall = io_pp_in_bits_pcall; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[exu_alu_ctl.scala 358:30]
assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_io_en = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[lib.scala 402:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_14 = _RAND_0[30:0];
_RAND_1 = {1{`RANDOM}};
_T_18 = _RAND_1[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_14 = 31'h0;
end
if (reset) begin
_T_18 = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_14 <= 31'h0;
end else if (io_enable) begin
_T_14 <= io_dec_i0_pc_d;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_18 <= 32'h0;
end else if (_T_15) begin
_T_18 <= result;
end
end
endmodule

23
exu_mul_ctl.anno.json Normal file
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@ -0,0 +1,23 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_mul_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_mul_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

40174
exu_mul_ctl.fir Normal file
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File diff suppressed because it is too large Load Diff

198
exu_mul_ctl.v Normal file
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@ -0,0 +1,198 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14]
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module exu_mul_ctl(
input clock,
input reset,
input io_scan_mode,
input io_mul_p_valid,
input io_mul_p_bits_rs1_sign,
input io_mul_p_bits_rs2_sign,
input io_mul_p_bits_low,
input io_mul_p_bits_bext,
input io_mul_p_bits_bdep,
input io_mul_p_bits_clmul,
input io_mul_p_bits_clmulh,
input io_mul_p_bits_clmulr,
input io_mul_p_bits_grev,
input io_mul_p_bits_gorc,
input io_mul_p_bits_shfl,
input io_mul_p_bits_unshfl,
input io_mul_p_bits_crc32_b,
input io_mul_p_bits_crc32_h,
input io_mul_p_bits_crc32_w,
input io_mul_p_bits_crc32c_b,
input io_mul_p_bits_crc32c_h,
input io_mul_p_bits_crc32c_w,
input io_mul_p_bits_bfp,
input [31:0] io_rs1_in,
input [31:0] io_rs2_in,
output [31:0] io_result_x
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[lib.scala 399:23]
wire rvclkhdr_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_io_en; // @[lib.scala 399:23]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 422:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 422:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 399:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_3_io_en; // @[lib.scala 399:23]
wire rvclkhdr_4_io_l1clk; // @[lib.scala 399:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_4_io_en; // @[lib.scala 399:23]
wire _T_1 = io_mul_p_bits_rs1_sign & io_rs1_in[31]; // @[exu_mul_ctl.scala 123:44]
wire _T_5 = io_mul_p_bits_rs2_sign & io_rs2_in[31]; // @[exu_mul_ctl.scala 124:44]
reg low_x; // @[Reg.scala 27:20]
reg [32:0] rs1_x; // @[lib.scala 428:16]
reg [32:0] rs2_x; // @[lib.scala 428:16]
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[exu_mul_ctl.scala 130:20]
wire _T_39758 = ~low_x; // @[exu_mul_ctl.scala 388:46]
wire [7:0] _T_39762 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758}; // @[Cat.scala 29:58]
wire [15:0] _T_39763 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39762}; // @[Cat.scala 29:58]
wire [31:0] _T_39764 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39762,_T_39763}; // @[Cat.scala 29:58]
wire [31:0] _T_39766 = _T_39764 & prod_x[63:32]; // @[exu_mul_ctl.scala 388:54]
wire [7:0] _T_39771 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x}; // @[Cat.scala 29:58]
wire [15:0] _T_39772 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771}; // @[Cat.scala 29:58]
wire [31:0] _T_39773 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771,_T_39772}; // @[Cat.scala 29:58]
wire [31:0] _T_39775 = _T_39773 & prod_x[31:0]; // @[exu_mul_ctl.scala 389:40]
rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 399:23]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 399:23]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
assign io_result_x = _T_39766 | _T_39775; // @[exu_mul_ctl.scala 388:15]
assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_io_en = io_mul_p_valid; // @[lib.scala 402:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
assign rvclkhdr_1_io_en = io_mul_p_valid; // @[lib.scala 425:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
assign rvclkhdr_2_io_en = io_mul_p_valid; // @[lib.scala 425:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_3_io_en = io_mul_p_valid; // @[lib.scala 402:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_4_io_en = io_mul_p_valid; // @[lib.scala 402:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
low_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
rs1_x = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
rs2_x = _RAND_2[32:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
low_x = 1'h0;
end
if (reset) begin
rs1_x = 33'sh0;
end
if (reset) begin
rs2_x = 33'sh0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
low_x <= 1'h0;
end else if (io_mul_p_valid) begin
low_x <= io_mul_p_bits_low;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
rs1_x <= 33'sh0;
end else begin
rs1_x <= {_T_1,io_rs1_in};
end
end
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
if (reset) begin
rs2_x <= 33'sh0;
end else begin
rs2_x <= {_T_5,io_rs2_in};
end
end
endmodule

602
src/main/scala/dec/dec.scala
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@ -1,301 +1,301 @@
package dec //package dec
import chisel3._ //import chisel3._
import chisel3.util._ //import chisel3.util._
import include._ //import include._
import lib._ //import lib._
import lsu._ //import lsu._
//
class dec_IO extends Bundle with lib { //class dec_IO extends Bundle with lib {
val free_clk = Input(Clock()) // val free_clk = Input(Clock())
val active_clk = Input(Clock()) // val active_clk = Input(Clock())
val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle // val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating // val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating
val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins // val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins
//
val nmi_int = Input(Bool()) // NMI pin // val nmi_int = Input(Bool()) // NMI pin
val nmi_vec = Input(UInt(31.W)) // [31:1] NMI vector, from pins // val nmi_vec = Input(UInt(31.W)) // [31:1] NMI vector, from pins
//
val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU // val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU
val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU // val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU
//
val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw) // val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw)
val o_cpu_halt_ack = Output(Bool()) // Halt request ack // val o_cpu_halt_ack = Output(Bool()) // Halt request ack
val o_cpu_run_ack = Output(Bool()) // Run request ack // val o_cpu_run_ack = Output(Bool()) // Run request ack
val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request // val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
//
val core_id = Input(UInt(28.W)) // [31:4] CORE ID // val core_id = Input(UInt(28.W)) // [31:4] CORE ID
//
val mpc_debug_halt_req = Input(Bool()) // Async halt request // val mpc_debug_halt_req = Input(Bool()) // Async halt request
val mpc_debug_run_req = Input(Bool()) // Async run request // val mpc_debug_run_req = Input(Bool()) // Async run request
val mpc_reset_run_req = Input(Bool()) // Run/halt after reset // val mpc_reset_run_req = Input(Bool()) // Run/halt after reset
val mpc_debug_halt_ack = Output(Bool()) // Halt ack // val mpc_debug_halt_ack = Output(Bool()) // Halt ack
val mpc_debug_run_ack = Output(Bool()) // Run ack // val mpc_debug_run_ack = Output(Bool()) // Run ack
val debug_brkpt_status = Output(Bool()) // debug breakpoint // val debug_brkpt_status = Output(Bool()) // debug breakpoint
val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned // val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned
//
//
val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address // val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address
val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error // val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error
//
val lsu_trigger_match_m = Input(UInt(4.W)) // val lsu_trigger_match_m = Input(UInt(4.W))
val lsu_idle_any = Input(Bool()) // lsu idle for halting // val lsu_idle_any = Input(Bool()) // lsu idle for halting
val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t)) // LSU exception/error packet // val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t)) // LSU exception/error packet
val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter // val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
val exu_div_result = Input(UInt(32.W)) // final div result // val exu_div_result = Input(UInt(32.W)) // final div result
val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR // val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR
val lsu_result_m = Input(UInt(32.W)) // load result // val lsu_result_m = Input(UInt(32.W)) // load result
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data // val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data
//
val lsu_load_stall_any = Input(Bool()) // This is for blocking loads // val lsu_load_stall_any = Input(Bool()) // This is for blocking loads
val lsu_store_stall_any = Input(Bool()) // This is for blocking stores // val lsu_store_stall_any = Input(Bool()) // This is for blocking stores
//
//
val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error // val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error
//
val exu_flush_final = Input(Bool()) // slot0 flush // val exu_flush_final = Input(Bool()) // slot0 flush
val timer_int = Input(Bool()) // Timer interrupt pending (from pin) // val timer_int = Input(Bool()) // Timer interrupt pending (from pin)
val soft_int = Input(Bool()) // Software interrupt pending (from pin) // val soft_int = Input(Bool()) // Software interrupt pending (from pin)
//
//
//
// Debug start // // Debug start
val dbg_halt_req = Input(Bool()) // DM requests a halt // val dbg_halt_req = Input(Bool()) // DM requests a halt
val dbg_resume_req = Input(Bool()) // DM requests a resume // val dbg_resume_req = Input(Bool()) // DM requests a resume
val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command // val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command
val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode // val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode
val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge // val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge
val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC // val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC
val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data // val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data
//
val dec_dbg_cmd_done = Output(Bool()) // abstract command is done // val dec_dbg_cmd_done = Output(Bool()) // abstract command is done
val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address) // val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address)
//
val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t)) // info needed by debug trigger blocks // val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t)) // info needed by debug trigger blocks
val exu_i0_br_way_r = Input(Bool()) // way hit or repl // val exu_i0_br_way_r = Input(Bool()) // way hit or repl
val lsu_p = Valid(new lsu_pkt_t) // lsu packet // val lsu_p = Valid(new lsu_pkt_t) // lsu packet
val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses // val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state // val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc // val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc // val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc // val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc // val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
val dec_lsu_valid_raw_d = Output(Bool()) // val dec_lsu_valid_raw_d = Output(Bool())
val rv_trace_pkt = (new trace_pkt_t) // trace packet // val rv_trace_pkt = (new trace_pkt_t) // trace packet
//
// clock gating overrides from mcgc // // clock gating overrides from mcgc
val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating // val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating
val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating // val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating
val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating // val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating
val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating // val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating
val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating // val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating
val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating // val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating // val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
//
val scan_mode = Input(Bool()) // val scan_mode = Input(Bool())
val ifu_dec = Flipped(new ifu_dec) // val ifu_dec = Flipped(new ifu_dec)
val dec_exu = Flipped(new dec_exu) // val dec_exu = Flipped(new dec_exu)
val lsu_dec = Flipped (new lsu_dec) // val lsu_dec = Flipped (new lsu_dec)
val lsu_tlu = Flipped (new lsu_tlu) // val lsu_tlu = Flipped (new lsu_tlu)
val dec_dbg = new dec_dbg // val dec_dbg = new dec_dbg
val dec_dma = new dec_dma // val dec_dma = new dec_dma
val dec_pic = new dec_pic // val dec_pic = new dec_pic
} //}
class dec extends Module with param with RequireAsyncReset{ //class dec extends Module with param with RequireAsyncReset{
val io = IO(new dec_IO) // val io = IO(new dec_IO)
//
val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U) // val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U)
val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U) // val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U)
val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U) // val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U)
val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U) // val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U)
//
val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U) // val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U)
val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U) // val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B) // val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
//
//
//--------------------------------------------------------------------------// // //--------------------------------------------------------------------------//
val instbuff = Module(new dec_ib_ctl) // val instbuff = Module(new dec_ib_ctl)
val decode = Module(new dec_decode_ctl) // val decode = Module(new dec_decode_ctl)
val gpr = Module(new dec_gpr_ctl) // val gpr = Module(new dec_gpr_ctl)
val tlu = Module(new dec_tlu_ctl) // val tlu = Module(new dec_tlu_ctl)
val dec_trigger = Module(new dec_trigger) // val dec_trigger = Module(new dec_trigger)
//
//connections for dec_Ib // //connections for dec_Ib
//inputs // //inputs
instbuff.io.ifu_ib <> io.ifu_dec.dec_aln.aln_ib // instbuff.io.ifu_ib <> io.ifu_dec.dec_aln.aln_ib
instbuff.io.ib_exu <> io.dec_exu.ib_exu // instbuff.io.ib_exu <> io.dec_exu.ib_exu
instbuff.io.dbg_ib <> io.dec_dbg.dbg_ib // instbuff.io.dbg_ib <> io.dec_dbg.dbg_ib
dec_trigger.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d // dec_trigger.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any // dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
//
val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d // val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
dontTouch(dec_i0_trigger_match_d) // dontTouch(dec_i0_trigger_match_d)
decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec // decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec
//
decode.io.decode_exu<> io.dec_exu.decode_exu // decode.io.decode_exu<> io.dec_exu.decode_exu
decode.io.dec_alu<> io.dec_exu.dec_alu // decode.io.dec_alu<> io.dec_exu.dec_alu
decode.io.dec_div<> io.dec_exu.dec_div // decode.io.dec_div<> io.dec_exu.dec_div
decode.io.dctl_dma <> io.dec_dma.dctl_dma // decode.io.dctl_dma <> io.dec_dma.dctl_dma
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint // decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt // decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt
decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff // decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff
decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d // decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r // decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable // decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable
decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m // decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m
decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_misaligned_m // decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_misaligned_m
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall // decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
decode.io.dec_tlu_flush_leak_one_r := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb // decode.io.dec_tlu_flush_leak_one_r := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb
decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d // decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d
decode.io.dbg_dctl <> io.dec_dbg.dbg_dctl // decode.io.dbg_dctl <> io.dec_dbg.dbg_dctl
decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d // decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d
decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d // decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d
decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d // decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d
decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d // decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d
decode.io.dec_i0_brp := instbuff.io.dec_i0_brp // decode.io.dec_i0_brp := instbuff.io.dec_i0_brp
decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index // decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index
decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr // decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr
decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag // decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag
decode.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d // decode.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
decode.io.lsu_idle_any := io.lsu_idle_any // decode.io.lsu_idle_any := io.lsu_idle_any
decode.io.lsu_load_stall_any := io.lsu_load_stall_any // decode.io.lsu_load_stall_any := io.lsu_load_stall_any
decode.io.lsu_store_stall_any := io.lsu_store_stall_any // decode.io.lsu_store_stall_any := io.lsu_store_stall_any
decode.io.exu_div_wren := io.exu_div_wren // decode.io.exu_div_wren := io.exu_div_wren
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb // decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb // decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r // decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r // decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r // decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d // decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d // decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d // decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d // decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d // decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
decode.io.lsu_result_m := io.lsu_result_m // decode.io.lsu_result_m := io.lsu_result_m
decode.io.lsu_result_corr_r := io.lsu_result_corr_r // decode.io.lsu_result_corr_r := io.lsu_result_corr_r
decode.io.exu_flush_final := io.exu_flush_final // decode.io.exu_flush_final := io.exu_flush_final
decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d // decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d // decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
decode.io.free_clk := io.free_clk // decode.io.free_clk := io.free_clk
decode.io.active_clk := io.active_clk // decode.io.active_clk := io.active_clk
decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override // decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
decode.io.scan_mode := io.scan_mode // decode.io.scan_mode := io.scan_mode
dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer // dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer
dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer // dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer
io.lsu_p := decode.io.lsu_p // io.lsu_p := decode.io.lsu_p
io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d // io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d
io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d // io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d
io.dec_pause_state_cg := decode.io.dec_pause_state_cg // io.dec_pause_state_cg := decode.io.dec_pause_state_cg
gpr.io.raddr0 := decode.io.dec_i0_rs1_d // gpr.io.raddr0 := decode.io.dec_i0_rs1_d
gpr.io.raddr1 := decode.io.dec_i0_rs2_d // gpr.io.raddr1 := decode.io.dec_i0_rs2_d
gpr.io.wen0 := decode.io.dec_i0_wen_r // gpr.io.wen0 := decode.io.dec_i0_wen_r
gpr.io.waddr0 := decode.io.dec_i0_waddr_r // gpr.io.waddr0 := decode.io.dec_i0_waddr_r
gpr.io.wd0 := decode.io.dec_i0_wdata_r // gpr.io.wd0 := decode.io.dec_i0_wdata_r
gpr.io.wen1 := decode.io.dec_nonblock_load_wen // gpr.io.wen1 := decode.io.dec_nonblock_load_wen
gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr // gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr
gpr.io.wd1 := io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data // gpr.io.wd1 := io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data
gpr.io.wen2 := io.exu_div_wren // gpr.io.wen2 := io.exu_div_wren
gpr.io.waddr2 := decode.io.div_waddr_wb // gpr.io.waddr2 := decode.io.div_waddr_wb
gpr.io.wd2 := io.exu_div_result // gpr.io.wd2 := io.exu_div_result
gpr.io.scan_mode := io.scan_mode // gpr.io.scan_mode := io.scan_mode
io.dec_exu.gpr_exu <> gpr.io.gpr_exu // io.dec_exu.gpr_exu <> gpr.io.gpr_exu
tlu.io.tlu_mem <> io.ifu_dec.dec_mem_ctrl // tlu.io.tlu_mem <> io.ifu_dec.dec_mem_ctrl
tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc // tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc
tlu.io.tlu_bp <> io.ifu_dec.dec_bp // tlu.io.tlu_bp <> io.ifu_dec.dec_bp
tlu.io.tlu_exu <> io.dec_exu.tlu_exu // tlu.io.tlu_exu <> io.dec_exu.tlu_exu
tlu.io.tlu_dma <> io.dec_dma.tlu_dma // tlu.io.tlu_dma <> io.dec_dma.tlu_dma
tlu.io.active_clk := io.active_clk // tlu.io.active_clk := io.active_clk
tlu.io.free_clk := io.free_clk // tlu.io.free_clk := io.free_clk
tlu.io.scan_mode := io.scan_mode // tlu.io.scan_mode := io.scan_mode
tlu.io.rst_vec := io.rst_vec // tlu.io.rst_vec := io.rst_vec
tlu.io.nmi_int := io.nmi_int // tlu.io.nmi_int := io.nmi_int
tlu.io.nmi_vec := io.nmi_vec // tlu.io.nmi_vec := io.nmi_vec
tlu.io.i_cpu_halt_req := io.i_cpu_halt_req // tlu.io.i_cpu_halt_req := io.i_cpu_halt_req
tlu.io.i_cpu_run_req := io.i_cpu_run_req // tlu.io.i_cpu_run_req := io.i_cpu_run_req
tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any // tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any
tlu.io.ifu_pmu_instr_aligned := io.ifu_dec.dec_aln.ifu_pmu_instr_aligned // tlu.io.ifu_pmu_instr_aligned := io.ifu_dec.dec_aln.ifu_pmu_instr_aligned
tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded // tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded
tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall // tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall
tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall // tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall // tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
tlu.io.lsu_store_stall_any := io.lsu_store_stall_any // tlu.io.lsu_store_stall_any := io.lsu_store_stall_any
io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff // io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff
io.lsu_tlu <> tlu.io.lsu_tlu // io.lsu_tlu <> tlu.io.lsu_tlu
io.dec_pic <> tlu.io.dec_pic // io.dec_pic <> tlu.io.dec_pic
tlu.io.lsu_fir_addr := io.lsu_fir_addr // tlu.io.lsu_fir_addr := io.lsu_fir_addr
tlu.io.lsu_fir_error := io.lsu_fir_error // tlu.io.lsu_fir_error := io.lsu_fir_error
tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error // tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error
tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r // tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr // tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
tlu.io.dec_pause_state := decode.io.dec_pause_state // tlu.io.dec_pause_state := decode.io.dec_pause_state
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d // tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d // tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d // tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r // tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r // tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r // tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff // tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r // tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r // tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r // tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst // tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
tlu.io.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d // tlu.io.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d
tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r // tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
tlu.io.dbg_halt_req := io.dbg_halt_req // tlu.io.dbg_halt_req := io.dbg_halt_req
tlu.io.dbg_resume_req := io.dbg_resume_req // tlu.io.dbg_resume_req := io.dbg_resume_req
tlu.io.lsu_idle_any := io.lsu_idle_any // tlu.io.lsu_idle_any := io.lsu_idle_any
tlu.io.dec_div_active := decode.io.dec_div_active // tlu.io.dec_div_active := decode.io.dec_div_active
tlu.io.timer_int := io.timer_int // tlu.io.timer_int := io.timer_int
tlu.io.soft_int := io.soft_int // tlu.io.soft_int := io.soft_int
tlu.io.core_id := io.core_id // tlu.io.core_id := io.core_id
tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req // tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req
tlu.io.mpc_debug_run_req := io.mpc_debug_run_req // tlu.io.mpc_debug_run_req := io.mpc_debug_run_req
tlu.io.mpc_reset_run_req := io.mpc_reset_run_req // tlu.io.mpc_reset_run_req := io.mpc_reset_run_req
io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done // io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done
io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail // io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail
io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted // io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted
io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode // io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode
io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack // io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack
io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only // io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only
io.trigger_pkt_any := tlu.io.trigger_pkt_any // io.trigger_pkt_any := tlu.io.trigger_pkt_any
io.o_cpu_halt_status := tlu.io.o_cpu_halt_status // io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack // io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
io.o_cpu_run_ack := tlu.io.o_cpu_run_ack // io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
io.o_debug_mode_status := tlu.io.o_debug_mode_status // io.o_debug_mode_status := tlu.io.o_debug_mode_status
io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack // io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack // io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
io.debug_brkpt_status := tlu.io.debug_brkpt_status // io.debug_brkpt_status := tlu.io.debug_brkpt_status
io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r // io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0 // io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1 // io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2 // io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2
io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3 // io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3
dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1 // dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1
dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1 // dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1
dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1 // dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1
dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1 // dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1
dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1 // dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1
io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override // io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override
io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override // io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override
io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override // io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override
io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override // io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override
io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override // io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override
io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override // io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override
io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override // io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override
//
//--------------------------------------------------------------------------// // //--------------------------------------------------------------------------//
//
io.rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb1 // io.rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb1
io.rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb1, 0.U) // io.rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb1, 0.U)
io.rv_trace_pkt.rv_i_valid_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1) // io.rv_trace_pkt.rv_i_valid_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1)
io.rv_trace_pkt.rv_i_exception_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) // io.rv_trace_pkt.rv_i_exception_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1)
io.rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0) // io.rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0)
io.rv_trace_pkt.rv_i_interrupt_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, 0.U) // io.rv_trace_pkt.rv_i_interrupt_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, 0.U)
io.rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1 // io.rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1
//
//
// debug command read data // // debug command read data
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r // io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
} //}
//
//

1570
src/main/scala/dec/dec_decode_ctl.scala
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153
src/main/scala/exu/exu.scala
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@ -25,6 +25,7 @@ class exu extends Module with lib with RequireAsyncReset{
val lsu_exu = Flipped(new lsu_exu()) val lsu_exu = Flipped(new lsu_exu())
//ifu_ifc //ifu_ifc
val exu_flush_path_final = Output(UInt(31.W)) // Target for the oldest flush source val exu_flush_path_final = Output(UInt(31.W)) // Target for the oldest flush source
val dec_qual_lsu_d = Input(Bool())
}) })
@ -35,9 +36,7 @@ class exu extends Module with lib with RequireAsyncReset{
val i0_taken_d = Wire(UInt(1.W)) val i0_taken_d = Wire(UInt(1.W))
val mul_valid_x = Wire(UInt(1.W)) val mul_valid_x = Wire(UInt(1.W))
val i0_valid_d = Wire(UInt(1.W)) val i0_valid_d = Wire(UInt(1.W))
val flush_lower_ff = Wire(UInt(1.W)) val i0_branch_x = Wire(UInt(1.W))
val data_gate_en = Wire(UInt(1.W))
val csr_rs1_in_d = Wire(UInt(32.W))
val i0_predict_newp_d = Wire(Valid(new predict_pkt_t())) val i0_predict_newp_d = Wire(Valid(new predict_pkt_t()))
val i0_flush_path_d = Wire(UInt(31.W)) val i0_flush_path_d = Wire(UInt(31.W))
val i0_predict_p_d = Wire(Valid(new predict_pkt_t())) val i0_predict_p_d = Wire(Valid(new predict_pkt_t()))
@ -52,54 +51,48 @@ class exu extends Module with lib with RequireAsyncReset{
io.exu_bp.exu_mp_pkt.bits.br_error := 0.U io.exu_bp.exu_mp_pkt.bits.br_error := 0.U
io.exu_bp.exu_mp_pkt.valid := 0.U io.exu_bp.exu_mp_pkt.valid := 0.U
i0_pp_r.bits.toffset := 0.U i0_pp_r.bits.toffset := 0.U
val x_data_en = io.dec_exu.decode_exu.dec_data_en(1) val x_data_en = io.dec_exu.decode_exu.dec_data_en(1)
val x_data_en_q1 = io.dec_exu.decode_exu.dec_data_en(1) & io.dec_exu.dec_alu.dec_csr_ren_d
val x_data_en_q2 = io.dec_exu.decode_exu.dec_data_en(1) & io.dec_exu.decode_exu.dec_i0_branch_d
val r_data_en = io.dec_exu.decode_exu.dec_data_en(0) val r_data_en = io.dec_exu.decode_exu.dec_data_en(0)
val r_data_en_q2 = io.dec_exu.decode_exu.dec_data_en(0) & i0_branch_x
val x_ctl_en = io.dec_exu.decode_exu.dec_ctl_en(1) val x_ctl_en = io.dec_exu.decode_exu.dec_ctl_en(1)
val r_ctl_en = io.dec_exu.decode_exu.dec_ctl_en(0) val r_ctl_en = io.dec_exu.decode_exu.dec_ctl_en(0)
val predpipe_d = Cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d, io.dec_exu.decode_exu.i0_predict_btag_d) val predpipe_d = Cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d, io.dec_exu.decode_exu.i0_predict_btag_d)
val i0_flush_path_x =rvdffpcie(i0_flush_path_d,x_data_en.asBool,reset.asAsyncReset,clock,io.scan_mode)
val i0_flush_path_x =rvdffe(i0_flush_path_d,x_data_en.asBool,clock,io.scan_mode) i0_predict_p_x :=rvdffppe(i0_predict_p_d,clock,reset.asAsyncReset,x_data_en.asBool,io.scan_mode,elements= 13,io.exu_bp.exu_mp_pkt.bits.pret)
io.dec_exu.decode_exu.exu_csr_rs1_x :=rvdffe(csr_rs1_in_d,x_data_en.asBool,clock,io.scan_mode) val predpipe_x =rvdffe(predpipe_d,x_data_en_q2.asBool,clock,io.scan_mode)
i0_predict_p_x :=rvdffe(i0_predict_p_d,x_data_en.asBool,clock,io.scan_mode) val predpipe_r =rvdffe(predpipe_x ,r_data_en_q2.asBool,clock,io.scan_mode)
val predpipe_x =rvdffe(predpipe_d,x_data_en.asBool,clock,io.scan_mode)
val predpipe_r =rvdffe(predpipe_x ,r_data_en.asBool,clock,io.scan_mode)
val ghr_x =rvdffe(ghr_x_ns ,x_ctl_en.asBool,clock,io.scan_mode) val ghr_x =rvdffe(ghr_x_ns ,x_ctl_en.asBool,clock,io.scan_mode)
val i0_pred_correct_upper_x =rvdffe(i0_pred_correct_upper_d ,x_ctl_en.asBool,clock,io.scan_mode) val i0_pred_correct_upper_x =rvdffe(i0_pred_correct_upper_d ,x_ctl_en.asBool,clock,io.scan_mode)
val i0_flush_upper_x =rvdffe(i0_flush_upper_d ,x_ctl_en.asBool,clock,io.scan_mode) val i0_flush_upper_x =rvdffe(i0_flush_upper_d ,x_ctl_en.asBool,clock,io.scan_mode)
val i0_taken_x =rvdffe(i0_taken_d ,x_ctl_en.asBool,clock,io.scan_mode) val i0_taken_x =rvdffe(i0_taken_d ,x_ctl_en.asBool,clock,io.scan_mode)
val i0_valid_x =rvdffe(i0_valid_d ,x_ctl_en.asBool,clock,io.scan_mode) val i0_valid_x =rvdffe(i0_valid_d ,x_ctl_en.asBool,clock,io.scan_mode)
i0_pp_r :=rvdffe(i0_predict_p_x,r_ctl_en.asBool,clock,io.scan_mode) i0_pp_r :=rvdffppe(i0_predict_p_x,clock,reset.asAsyncReset(),r_ctl_en.asBool,io.scan_mode,elements = 13,io.exu_bp.exu_mp_pkt.bits.pret)
val pred_temp1 =rvdffe(io.dec_exu.decode_exu.pred_correct_npc_x(5,0) ,r_ctl_en.asBool,clock,io.scan_mode) val pred_temp1 =rvdffpcie(io.dec_exu.decode_exu.pred_correct_npc_x(5,0) ,r_data_en.asBool,reset.asAsyncReset(),clock,io.scan_mode)
val i0_pred_correct_upper_r =rvdffe(i0_pred_correct_upper_x ,r_ctl_en.asBool,clock,io.scan_mode) val i0_pred_correct_upper_r =rvdffppe_UInt(i0_pred_correct_upper_x ,clock,reset.asAsyncReset(),r_ctl_en.asBool,io.scan_mode,WIDTH=1)
val i0_flush_path_upper_r =rvdffe(i0_flush_path_x ,r_data_en.asBool,clock,io.scan_mode) val i0_flush_path_upper_r =rvdffpcie(i0_flush_path_x ,r_data_en.asBool,reset.asAsyncReset(),clock,io.scan_mode)
val pred_temp2 =rvdffe(io.dec_exu.decode_exu.pred_correct_npc_x(30,6) ,r_data_en.asBool,clock,io.scan_mode) val pred_temp2 =rvdffpcie(io.dec_exu.decode_exu.pred_correct_npc_x(30,6) ,r_data_en.asBool,reset.asAsyncReset(),clock,io.scan_mode)
pred_correct_npc_r :=Cat(pred_temp2,pred_temp1) pred_correct_npc_r :=Cat(pred_temp2,pred_temp1)
ghr_d :=rvdffie(ghr_d_ns,clock,reset.asAsyncReset(),io.scan_mode)
mul_valid_x :=rvdffie(io.dec_exu.decode_exu.mul_p.valid,clock,reset.asAsyncReset(),io.scan_mode)
i0_branch_x :=rvdffie(io.dec_exu.decode_exu.dec_i0_branch_d,clock,reset.asAsyncReset(),io.scan_mode)
when (BHT_SIZE.asUInt===32.U || BHT_SIZE.asUInt===64.U){ val i0_rs1_bypass_en_d = io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0) | io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1) | io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(2) | io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(3)
ghr_d :=RegEnable(ghr_d_ns,0.U,data_gate_en.asBool) val i0_rs2_bypass_en_d = io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0) | io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1) | io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(2) | io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(3)
mul_valid_x :=RegEnable(io.dec_exu.decode_exu.mul_p.valid,0.U,data_gate_en.asBool)
flush_lower_ff :=RegEnable(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r,0.U,data_gate_en.asBool)
}.otherwise{
ghr_d :=rvdffe(ghr_d_ns ,data_gate_en.asBool,clock,io.scan_mode)
mul_valid_x :=rvdffe(io.dec_exu.decode_exu.mul_p.valid ,data_gate_en.asBool,clock,io.scan_mode)
flush_lower_ff :=rvdffe(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r ,data_gate_en.asBool,clock,io.scan_mode)
}
data_gate_en := (ghr_d_ns =/= ghr_d) | ( io.dec_exu.decode_exu.mul_p.valid =/= mul_valid_x) | ( io.dec_exu.tlu_exu.dec_tlu_flush_lower_r =/= flush_lower_ff)
val i0_rs1_bypass_en_d = io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0) | io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1)
val i0_rs2_bypass_en_d = io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0) | io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1)
val i0_rs1_bypass_data_d = Mux1H(Seq( val i0_rs1_bypass_data_d = Mux1H(Seq(
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d, io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_result_r,
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1).asBool -> io.dec_exu.decode_exu.exu_i0_result_x io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1).asBool -> io.lsu_exu.lsu_result_m,
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(2).asBool -> io.dec_exu.decode_exu.exu_i0_result_x,
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(3).asBool -> io.lsu_exu.lsu_nonblock_load_data
)) ))
val i0_rs2_bypass_data_d = Mux1H(Seq( val i0_rs2_bypass_data_d = Mux1H(Seq(
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d, io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_result_r,
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1).asBool -> io.dec_exu.decode_exu.exu_i0_result_x io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1).asBool -> io.lsu_exu.lsu_result_m,
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(2).asBool -> io.dec_exu.decode_exu.exu_i0_result_x,
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(3).asBool -> io.lsu_exu.lsu_nonblock_load_data
)) ))
val i0_rs1_d = Mux1H(Seq( val i0_rs1_d = Mux1H(Seq(
@ -108,6 +101,7 @@ class exu extends Module with lib with RequireAsyncReset{
(!i0_rs1_bypass_en_d & io.dec_exu.ib_exu.dec_debug_wdata_rs1_d).asBool -> io.dbg_cmd_wrdata, (!i0_rs1_bypass_en_d & io.dec_exu.ib_exu.dec_debug_wdata_rs1_d).asBool -> io.dbg_cmd_wrdata,
(!i0_rs1_bypass_en_d & !io.dec_exu.ib_exu.dec_debug_wdata_rs1_d & io.dec_exu.decode_exu.dec_i0_rs1_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d (!i0_rs1_bypass_en_d & !io.dec_exu.ib_exu.dec_debug_wdata_rs1_d & io.dec_exu.decode_exu.dec_i0_rs1_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d
)) ))
io.dec_exu.decode_exu.exu_csr_rs1_x :=rvdffe(i0_rs1_d,x_data_en_q1.asBool,clock,io.scan_mode)
val i0_rs2_d = Mux1H(Seq( val i0_rs2_d = Mux1H(Seq(
(!i0_rs2_bypass_en_d & io.dec_exu.decode_exu.dec_i0_rs2_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d, (!i0_rs2_bypass_en_d & io.dec_exu.decode_exu.dec_i0_rs2_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
@ -117,14 +111,14 @@ class exu extends Module with lib with RequireAsyncReset{
dontTouch(i0_rs2_d) dontTouch(i0_rs2_d)
io.lsu_exu.exu_lsu_rs1_d:=Mux1H(Seq( io.lsu_exu.exu_lsu_rs1_d:=Mux1H(Seq(
(!i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs1_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d, (!i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs1_en_d & io.dec_qual_lsu_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d,
(i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall).asBool -> i0_rs1_bypass_data_d, (i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_qual_lsu_d).asBool -> i0_rs1_bypass_data_d,
(io.dec_exu.decode_exu.dec_extint_stall).asBool -> Cat(io.dec_exu.tlu_exu.dec_tlu_meihap,0.U(2.W)) (io.dec_exu.decode_exu.dec_extint_stall & io.dec_qual_lsu_d).asBool -> Cat(io.dec_exu.tlu_exu.dec_tlu_meihap,0.U(2.W))
)) ))
io.lsu_exu.exu_lsu_rs2_d:=Mux1H(Seq( io.lsu_exu.exu_lsu_rs2_d:=Mux1H(Seq(
(!i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs2_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d, (!i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs2_en_d & io.dec_qual_lsu_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
(i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall).asBool -> i0_rs2_bypass_data_d (i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_qual_lsu_d).asBool -> i0_rs2_bypass_data_d
)) ))
val muldiv_rs1_d=Mux1H(Seq( val muldiv_rs1_d=Mux1H(Seq(
@ -132,19 +126,10 @@ class exu extends Module with lib with RequireAsyncReset{
(i0_rs1_bypass_en_d).asBool -> i0_rs1_bypass_data_d (i0_rs1_bypass_en_d).asBool -> i0_rs1_bypass_data_d
)) ))
val muldiv_rs2_d=Mux1H(Seq(
(!i0_rs2_bypass_en_d & io.dec_exu.decode_exu.dec_i0_rs2_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
(!i0_rs2_bypass_en_d).asBool -> io.dec_exu.decode_exu.dec_i0_immed_d,
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
))
csr_rs1_in_d := Mux(io.dec_exu.dec_alu.dec_csr_ren_d.asBool, i0_rs1_d, io.dec_exu.decode_exu.exu_csr_rs1_x)
val i_alu=Module(new exu_alu_ctl()) val i_alu=Module(new exu_alu_ctl())
i_alu.io.dec_alu <> io.dec_exu.dec_alu i_alu.io.dec_alu <> io.dec_exu.dec_alu
i_alu.io.scan_mode :=io.scan_mode i_alu.io.scan_mode :=io.scan_mode
i_alu.io.enable :=x_ctl_en i_alu.io.enable :=x_data_en
i_alu.io.pp_in :=i0_predict_newp_d i_alu.io.pp_in :=i0_predict_newp_d
i_alu.io.flush_upper_x :=i0_flush_upper_x i_alu.io.flush_upper_x :=i0_flush_upper_x
i_alu.io.dec_tlu_flush_lower_r :=io.dec_exu.tlu_exu.dec_tlu_flush_lower_r i_alu.io.dec_tlu_flush_lower_r :=io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
@ -161,17 +146,16 @@ class exu extends Module with lib with RequireAsyncReset{
val i_mul = Module(new exu_mul_ctl()) val i_mul = Module(new exu_mul_ctl())
i_mul.io.scan_mode := io.scan_mode i_mul.io.scan_mode := io.scan_mode
i_mul.io.mul_p := io.dec_exu.decode_exu.mul_p i_mul.io.mul_p := io.dec_exu.decode_exu.mul_p // & Fill(io.dec_exu.decode_exu.mul_p.getWidth,io.dec_exu.decode_exu.mul_p.valid)
i_mul.io.rs1_in := muldiv_rs1_d i_mul.io.rs1_in := muldiv_rs1_d & Fill(32,io.dec_exu.decode_exu.mul_p.valid)
i_mul.io.rs2_in := muldiv_rs2_d i_mul.io.rs2_in := i0_rs2_d & Fill(32,io.dec_exu.decode_exu.mul_p.valid)
val mul_result_x = i_mul.io.result_x val mul_result_x = i_mul.io.result_x
val i_div = Module(new exu_div_ctl()) val i_div = Module(new exu_div_ctl())
i_div.io.dec_div <> io.dec_exu.dec_div i_div.io.dec_div <> io.dec_exu.dec_div
i_div.io.scan_mode := io.scan_mode i_div.io.scan_mode := io.scan_mode
i_div.io.dividend := muldiv_rs1_d i_div.io.dividend := muldiv_rs1_d
i_div.io.divisor := muldiv_rs2_d i_div.io.divisor := i0_rs2_d
io.exu_div_wren := i_div.io.exu_div_wren io.exu_div_wren := i_div.io.exu_div_wren
io.exu_div_result := i_div.io.exu_div_result io.exu_div_result := i_div.io.exu_div_result
@ -188,33 +172,33 @@ class exu extends Module with lib with RequireAsyncReset{
i0_taken_d := (i0_predict_p_d.bits.ataken & io.dec_exu.dec_alu.dec_i0_alu_decode_d) i0_taken_d := (i0_predict_p_d.bits.ataken & io.dec_exu.dec_alu.dec_i0_alu_decode_d)
if(BTB_ENABLE) {
// maintain GHR at D // maintain GHR at D
ghr_d_ns:=Mux1H(Seq( ghr_d_ns := Mux1H(Seq(
(!io.dec_exu.tlu_exu.dec_tlu_flush_lower_r & i0_valid_d).asBool -> Cat(ghr_d(BHT_GHR_SIZE-2,0),i0_taken_d), (!io.dec_exu.tlu_exu.dec_tlu_flush_lower_r & i0_valid_d).asBool -> Cat(ghr_d(BHT_GHR_SIZE - 2, 0), i0_taken_d),
(!io.dec_exu.tlu_exu.dec_tlu_flush_lower_r & !i0_valid_d).asBool -> ghr_d, (!io.dec_exu.tlu_exu.dec_tlu_flush_lower_r & !i0_valid_d).asBool -> ghr_d,
(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r).asBool -> ghr_x (io.dec_exu.tlu_exu.dec_tlu_flush_lower_r).asBool -> ghr_x
)) ))
// maintain GHR at X // maintain GHR at X
ghr_x_ns:=Mux(i0_valid_x===1.U, Cat(ghr_x(BHT_GHR_SIZE-2,0),i0_taken_x), ghr_x ) ghr_x_ns := Mux(i0_valid_x === 1.U, Cat(ghr_x(BHT_GHR_SIZE - 2, 0), i0_taken_x), ghr_x)
io.dec_exu.tlu_exu.exu_i0_br_valid_r := i0_pp_r.valid io.dec_exu.tlu_exu.exu_i0_br_valid_r := i0_pp_r.valid
io.dec_exu.tlu_exu.exu_i0_br_mp_r := i0_pp_r.bits.misp io.dec_exu.tlu_exu.exu_i0_br_mp_r := i0_pp_r.bits.misp
io.exu_bp.exu_i0_br_way_r := i0_pp_r.bits.way io.exu_bp.exu_i0_br_way_r := i0_pp_r.bits.way
io.dec_exu.tlu_exu.exu_i0_br_hist_r := i0_pp_r.bits.hist io.dec_exu.tlu_exu.exu_i0_br_hist_r := Fill(2, i0_pp_r.valid) & i0_pp_r.bits.hist
io.dec_exu.tlu_exu.exu_i0_br_error_r := i0_pp_r.bits.br_error io.dec_exu.tlu_exu.exu_i0_br_error_r := i0_pp_r.bits.br_error
io.dec_exu.tlu_exu.exu_i0_br_middle_r := i0_pp_r.bits.pc4 ^ i0_pp_r.bits.boffset io.dec_exu.tlu_exu.exu_i0_br_middle_r := i0_pp_r.bits.pc4 ^ i0_pp_r.bits.boffset
io.dec_exu.tlu_exu.exu_i0_br_start_error_r := i0_pp_r.bits.br_start_error io.dec_exu.tlu_exu.exu_i0_br_start_error_r := i0_pp_r.bits.br_start_error
io.exu_bp.exu_i0_br_fghr_r := predpipe_r(PREDPIPESIZE-1,BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO+1) io.exu_bp.exu_i0_br_fghr_r := predpipe_r(PREDPIPESIZE - 1, BTB_ADDR_HI + BTB_BTAG_SIZE - BTB_ADDR_LO + 1)
io.dec_exu.tlu_exu.exu_i0_br_index_r := predpipe_r(BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO,BTB_BTAG_SIZE) io.dec_exu.tlu_exu.exu_i0_br_index_r := predpipe_r(BTB_ADDR_HI + BTB_BTAG_SIZE - BTB_ADDR_LO, BTB_BTAG_SIZE)
io.exu_bp.exu_i0_br_index_r := io.dec_exu.tlu_exu.exu_i0_br_index_r io.exu_bp.exu_i0_br_index_r := io.dec_exu.tlu_exu.exu_i0_br_index_r
final_predict_mp := Mux(i0_flush_upper_x===1.U,i0_predict_p_x,0.U.asTypeOf(i0_predict_p_x)) final_predict_mp := Mux(i0_flush_upper_x === 1.U, i0_predict_p_x, 0.U.asTypeOf(i0_predict_p_x))
val final_predpipe_mp = Mux(i0_flush_upper_x===1.U,predpipe_x,0.U) val final_predpipe_mp = Mux(i0_flush_upper_x === 1.U, predpipe_x, 0.U)
val after_flush_eghr = Mux((i0_flush_upper_x===1.U & !(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r===1.U)), ghr_d, ghr_x)
val after_flush_eghr = Mux((i0_flush_upper_x === 1.U & !(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r === 1.U)), ghr_d, ghr_x)
io.exu_bp.exu_mp_pkt.valid := final_predict_mp.valid
io.exu_bp.exu_mp_pkt.bits.way := final_predict_mp.bits.way io.exu_bp.exu_mp_pkt.bits.way := final_predict_mp.bits.way
io.exu_bp.exu_mp_pkt.bits.misp := final_predict_mp.bits.misp io.exu_bp.exu_mp_pkt.bits.misp := final_predict_mp.bits.misp
io.exu_bp.exu_mp_pkt.bits.pcall := final_predict_mp.bits.pcall io.exu_bp.exu_mp_pkt.bits.pcall := final_predict_mp.bits.pcall
@ -223,13 +207,38 @@ class exu extends Module with lib with RequireAsyncReset{
io.exu_bp.exu_mp_pkt.bits.ataken := final_predict_mp.bits.ataken io.exu_bp.exu_mp_pkt.bits.ataken := final_predict_mp.bits.ataken
io.exu_bp.exu_mp_pkt.bits.boffset := final_predict_mp.bits.boffset io.exu_bp.exu_mp_pkt.bits.boffset := final_predict_mp.bits.boffset
io.exu_bp.exu_mp_pkt.bits.pc4 := final_predict_mp.bits.pc4 io.exu_bp.exu_mp_pkt.bits.pc4 := final_predict_mp.bits.pc4
io.exu_bp.exu_mp_pkt.bits.hist := final_predict_mp.bits.hist(1,0) io.exu_bp.exu_mp_pkt.bits.hist := final_predict_mp.bits.hist(1, 0)
io.exu_bp.exu_mp_pkt.bits.toffset := final_predict_mp.bits.toffset(11,0) io.exu_bp.exu_mp_pkt.bits.toffset := final_predict_mp.bits.toffset(11, 0)
io.exu_bp.exu_mp_fghr := after_flush_eghr io.exu_bp.exu_mp_fghr := after_flush_eghr
io.exu_bp.exu_mp_index := final_predpipe_mp(PREDPIPESIZE-BHT_GHR_SIZE-1,BTB_BTAG_SIZE) io.exu_bp.exu_mp_index := final_predpipe_mp(PREDPIPESIZE - BHT_GHR_SIZE - 1, BTB_BTAG_SIZE)
io.exu_bp.exu_mp_btag := final_predpipe_mp(BTB_BTAG_SIZE-1,0) io.exu_bp.exu_mp_btag := final_predpipe_mp(BTB_BTAG_SIZE - 1, 0)
io.exu_bp.exu_mp_eghr := final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write io.exu_bp.exu_mp_eghr := final_predpipe_mp(PREDPIPESIZE - 1, BTB_ADDR_HI - BTB_ADDR_LO + BTB_BTAG_SIZE + 1) // mp ghr for bht write
io.exu_flush_path_final := Mux(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d) }
else {
ghr_d_ns := 0.U
ghr_x_ns := 0.U
io.exu_bp.exu_mp_pkt := 0.U
io.exu_bp.exu_mp_eghr := 0.U
io.exu_bp.exu_mp_fghr := 0.U
io.exu_bp.exu_mp_index := 0.U
io.exu_bp.exu_mp_btag := 0.U
io.dec_exu.tlu_exu.exu_i0_br_hist_r := 0.U
io.dec_exu.tlu_exu.exu_i0_br_error_r := 0.U
io.dec_exu.tlu_exu.exu_i0_br_start_error_r := 0.U
io.dec_exu.tlu_exu.exu_i0_br_index_r := 0.U
io.dec_exu.tlu_exu.exu_i0_br_valid_r := 0.U
io.dec_exu.tlu_exu.exu_i0_br_mp_r := 0.U
io.dec_exu.tlu_exu.exu_i0_br_middle_r := 0.U
io.exu_bp.exu_i0_br_fghr_r := 0.U
io.exu_bp.exu_i0_br_way_r := 0.U
}
io.exu_flush_path_final := Mux1H(Seq(
io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool -> io.dec_exu.tlu_exu.dec_tlu_flush_path_r,
(~io.dec_exu.tlu_exu.dec_tlu_flush_lower_r & i0_flush_upper_d).asBool -> i0_flush_path_d))
io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r) io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r)
} }
object exu_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new exu()))
}

279
src/main/scala/exu/exu_alu_ctl.scala
View File

@ -9,6 +9,7 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
val io = IO(new Bundle{ val io = IO(new Bundle{
val dec_alu = new dec_alu() val dec_alu = new dec_alu()
//val csr_rddata_in = Input(UInt(32.W)) // CSR data
val dec_i0_pc_d = Input(UInt(31.W)) // for pc=pc+2,4 calculations val dec_i0_pc_d = Input(UInt(31.W)) // for pc=pc+2,4 calculations
val scan_mode = Input(UInt(1.W)) // Scan control val scan_mode = Input(UInt(1.W)) // Scan control
val flush_upper_x = Input(UInt(1.W)) // Branch flush from previous cycle val flush_upper_x = Input(UInt(1.W)) // Branch flush from previous cycle
@ -26,15 +27,123 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
val pred_correct_out = Output(UInt(1.W)) // NPC control val pred_correct_out = Output(UInt(1.W)) // NPC control
val predict_p_out = Valid(new predict_pkt_t) // Predicted branch structure val predict_p_out = Valid(new predict_pkt_t) // Predicted branch structure
}) })
//zbb
val ap_clz = WireInit(Bool(),0.B)
val ap_ctz = WireInit(Bool(),0.B)
val ap_pcnt = WireInit(Bool(),0.B)
val ap_sext_b = WireInit(Bool(),0.B)
val ap_sext_h = WireInit(Bool(),0.B)
val ap_min = WireInit(Bool(),0.B)
val ap_max = WireInit(Bool(),0.B)
val ap_pack = WireInit(Bool(),0.B)
val ap_packu = WireInit(Bool(),0.B)
val ap_packh = WireInit(Bool(),0.B)
val ap_rol = WireInit(Bool(),0.B)
val ap_ror = WireInit(Bool(),0.B)
val ap_rev = WireInit(Bool(),0.B)
val ap_rev8 = WireInit(Bool(),0.B)
val ap_orc_b = WireInit(Bool(),0.B)
val ap_orc16 = WireInit(Bool(),0.B)
val ap_zbb = WireInit(Bool(),0.B)
// Zbs
val ap_sbset = WireInit(Bool(),0.B)
val ap_sbclr = WireInit(Bool(),0.B)
val ap_sbinv = WireInit(Bool(),0.B)
val ap_sbext = WireInit(Bool(),0.B)
io.dec_alu.exu_i0_pc_x := rvdffe(io.dec_i0_pc_d,io.enable,clock,io.scan_mode.asBool) // any PC is run through here - doesn't have to be alu // Zbr
val ap_slo = WireInit(Bool(),0.B)
val ap_sro = WireInit(Bool(),0.B)
// Zba
val ap_sh1add = WireInit(Bool(),0.B)
val ap_sh2add = WireInit(Bool(),0.B)
val ap_sh3add = WireInit(Bool(),0.B)
val ap_zba = WireInit(Bool(),0.B)
if (BITMANIP_ZBB) {
ap_clz := io.i0_ap.clz
ap_ctz := io.i0_ap.ctz
ap_pcnt := io.i0_ap.pcnt
ap_sext_b := io.i0_ap.sext_b
ap_sext_h := io.i0_ap.sext_h
ap_min := io.i0_ap.min
ap_max := io.i0_ap.max
} else{
ap_clz := 0.U
ap_ctz := 0.U
ap_pcnt := 0.U
ap_sext_b := 0.U
ap_sext_h := 0.U
ap_min := 0.U
ap_max := 0.U
}
if ( (BITMANIP_ZBB) | (BITMANIP_ZBP) ) {
ap_pack := io.i0_ap.pack
ap_packu := io.i0_ap.packu
ap_packh := io.i0_ap.packh
ap_rol := io.i0_ap.rol
ap_ror := io.i0_ap.ror
ap_rev := io.i0_ap.grev & (io.b_in(4,0) === "b11111".U)
ap_rev8 := io.i0_ap.grev & (io.b_in(4,0) === "b11000".U)
ap_orc_b := io.i0_ap.gorc & (io.b_in(4,0) === "b00111".U)
ap_orc16 := io.i0_ap.gorc & (io.b_in(4,0) === "b10000".U)
ap_zbb := io.i0_ap.zbb
} else{
ap_pack := 0.U
ap_packu := 0.U
ap_packh := 0.U
ap_rol := 0.U
ap_ror := 0.U
ap_rev := 0.U
ap_rev8 := 0.U
ap_orc_b := 0.U
ap_orc16 := 0.U
ap_zbb := 0.U
}
if (BITMANIP_ZBS) {
ap_sbset := io.i0_ap.sbset
ap_sbclr := io.i0_ap.sbclr
ap_sbinv := io.i0_ap.sbinv
ap_sbext := io.i0_ap.sbext
}else {
ap_sbset := 0.U
ap_sbclr := 0.U
ap_sbinv := 0.U
ap_sbext := 0.U
}
if (BITMANIP_ZBP) {
ap_slo := io.i0_ap.slo
ap_sro := io.i0_ap.sro
} else {
ap_slo := 0.U
ap_sro := 0.U
}
if (BITMANIP_ZBA) {
ap_sh1add := io.i0_ap.sh1add
ap_sh2add := io.i0_ap.sh2add
ap_sh3add := io.i0_ap.sh3add
ap_zba := io.i0_ap.zba
} else {
ap_sh1add := 0.U
ap_sh2add := 0.U
ap_sh3add := 0.U
ap_zba := 0.U
}
io.dec_alu.exu_i0_pc_x := rvdffpcie(io.dec_i0_pc_d,io.enable,reset.asAsyncReset(),clock,io.scan_mode.asBool) // any PC is run through here - doesn't have to be alu
val result = WireInit(UInt(32.W),0.U) val result = WireInit(UInt(32.W),0.U)
io.result_ff := rvdffe(result,io.enable,clock,io.scan_mode.asBool) io.result_ff := rvdffe(result,io.enable & io.dec_alu.dec_i0_alu_decode_d,clock,io.scan_mode.asBool)
val zba_a_in = Mux1H(Seq(
ap_sh1add -> Cat(io.a_in(30,0),0.U(1.W)).asSInt ,
ap_sh2add -> Cat(io.a_in(29,0),0.U(2.W)).asSInt ,
ap_sh3add -> Cat(io.a_in(28,0),0.U(3.W)).asSInt ,
~ap_zba -> io.a_in ))
val bm = Mux( io.i0_ap.sub.asBool, ~io.b_in, io.b_in) //H:b modified val bm = Mux( io.i0_ap.sub.asBool, ~io.b_in, io.b_in) //H:b modified
val aout = WireInit(UInt(33.W),0.U) val aout = WireInit(UInt(33.W),0.U)
aout := Mux(io.i0_ap.sub.asBool,(Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W),~io.b_in) + Cat(0.U(32.W),io.i0_ap.sub)), (Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W), io.b_in) + Cat(0.U(32.W),io.i0_ap.sub))) aout := Mux(io.i0_ap.sub.asBool,(Cat(0.U(1.W),zba_a_in) + Cat(0.U(1.W),~io.b_in) + Cat(0.U(32.W),io.i0_ap.sub)), (Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W), io.b_in) + Cat(0.U(32.W),io.i0_ap.sub)))
val cout = aout(32) val cout = aout(32)
val ov = (!io.a_in(31) & !bm(31) & aout(31)) | ( io.a_in(31) & bm(31) & !aout(31) ) //overflow check from last bits val ov = (!io.a_in(31) & !bm(31) & aout(31)) | ( io.a_in(31) & bm(31) & !aout(31) ) //overflow check from last bits
@ -47,30 +156,142 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
val lout = Mux1H(Seq( val lout = Mux1H(Seq(
io.dec_alu.dec_csr_ren_d.asBool -> io.b_in.asSInt, //read enable read rs2 io.dec_alu.dec_csr_ren_d -> io.dec_alu.dec_csr_rddata_d.asSInt ,
io.i0_ap.land.asBool -> (io.a_in & io.b_in.asSInt), //and rs1 and 2 (io.i0_ap.land & !ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt & io.b_in.asSInt) ,
io.i0_ap.lor.asBool -> (io.a_in | io.b_in.asSInt), (io.i0_ap.lor & !ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt | io.b_in.asSInt) ,
io.i0_ap.lxor.asBool -> (io.a_in ^ io.b_in.asSInt))) (io.i0_ap.lxor & !ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt ^ io.b_in.asSInt) ,
(io.i0_ap.land & ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt & ~io.b_in.asSInt) ,
(io.i0_ap.lor & ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt | ~io.b_in.asSInt) ,
(io.i0_ap.lxor & ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt ^ ~io.b_in.asSInt) ))
// val lout = Mux1H(Seq(
// io.dec_alu.dec_csr_ren_d.asBool -> io.b_in.asSInt, //read enable read rs2
// io.i0_ap.land.asBool -> (io.a_in & io.b_in.asSInt), //and rs1 and 2
// io.i0_ap.lor.asBool -> (io.a_in | io.b_in.asSInt),
// io.i0_ap.lxor.asBool -> (io.a_in ^ io.b_in.asSInt)))
// * * * * * * * * * * * * * * * * * * BitManip : SLO,SRO * * * * * * * * * * * * * * * * * *
// * * * * * * * * * * * * * * * * * * BitManip : ROL,ROR * * * * * * * * * * * * * * * * * *
// * * * * * * * * * * * * * * * * * * BitManip : ZBEXT * * * * * * * * * * * * * * * * * *
val shift_amount = Mux1H(Seq ( val shift_amount = Mux1H(Seq (
io.i0_ap.sll.asBool -> (32.U(6.W) - Cat(0.U(1.W),io.b_in(4,0))), // [5] unused io.i0_ap.sll.asBool -> (32.U(6.W) - Cat(0.U(1.W),io.b_in(4,0))), // [5] unused
io.i0_ap.srl.asBool -> Cat(0.U(1.W),io.b_in(4,0)) , io.i0_ap.srl.asBool -> Cat(0.U(1.W),io.b_in(4,0)) ,
io.i0_ap.sra.asBool -> Cat(0.U(1.W),io.b_in(4,0)) )) io.i0_ap.sra.asBool -> Cat(0.U(1.W),io.b_in(4,0)) ,
ap_rol -> (32.U(6.W) - Cat(0.U(1.W),io.b_in(4,0)) ) ,
ap_ror -> Cat(0.U(1.W),io.b_in(4,0)) ,
ap_slo -> (32.U(6.W) - Cat(0.U(1.W),io.b_in(4,0)) ) ,
ap_sro -> Cat(0.U(1.W),io.b_in(4,0)) ,
ap_sbext -> Cat(0.U(1.W),io.b_in(4,0)) ))
val shift_mask = WireInit(UInt(32.W),0.U) val shift_mask = WireInit(UInt(32.W),0.U)
shift_mask := ( "hffffffff".U(32.W) << (repl(5,io.i0_ap.sll) & io.b_in(4,0)) ) shift_mask := ( "hffffffff".U(32.W) << (repl(5,io.i0_ap.sll | ap_slo) & io.b_in(4,0)) )
val shift_extend = WireInit(UInt(63.W),0.U) val shift_extend = WireInit(UInt(63.W),0.U)
shift_extend := Cat((repl(31,io.i0_ap.sra) & repl(31,io.a_in(31))) | (repl(31,io.i0_ap.sll) & io.a_in(30,0)),io.a_in) shift_extend := Cat((repl(31,io.i0_ap.sra) & repl(31,io.a_in(31))) | (repl(31,io.i0_ap.sll) & io.a_in(30,0)), io.a_in)
shift_extend := Cat( Mux1H(Seq(io.i0_ap.sra.asBool() -> Fill(31,io.a_in(31)) ,
io.i0_ap.sll.asBool() -> io.a_in(30,0) ,
ap_rol -> io.a_in(30,0) ,
ap_ror -> io.a_in(30,0) ,
ap_slo -> io.a_in(30,0) ,
ap_sro -> Fill(31,1.U) )),io.a_in)
val shift_long = WireInit(UInt(63.W),0.U) val shift_long = WireInit(UInt(63.W),0.U)
shift_long := ( shift_extend >> shift_amount(4,0) ); // 62-32 unused shift_long := ( shift_extend >> shift_amount(4,0) ) // 62-32 unused
val sout = ( shift_long(31,0) & shift_mask(31,0) ); //incase of sra shift_mask is 1 val sout = ( shift_long(31,0) & shift_mask(31,0) ) | ( Fill(32,ap_slo) & ~shift_mask(31,0) ) //incase of sra shift_mask is 1
// * * * * * * * * * * * * * * * * * * BitManip : CLZ,CTZ * * * * * * * * * * * * * * * * * *
val bitmanip_a_reverse_ff = (0 until io.a_in.getWidth).map(i=> io.a_in(i).asUInt).reduce(Cat(_,_))
// {a_in[0], a_in[1], a_in[2], a_in[3], a_in[4], a_in[5], a_in[6], a_in[7],
// a_in[8], a_in[9], a_in[10], a_in[11], a_in[12], a_in[13], a_in[14], a_in[15],
// a_in[16], a_in[17], a_in[18], a_in[19], a_in[20], a_in[21], a_in[22], a_in[23],
// a_in[24], a_in[25], a_in[26], a_in[27], a_in[28], a_in[29], a_in[30], a_in[31]};
val bitmanip_lzd_in = Mux1H(Seq(ap_clz -> io.a_in, ap_ctz -> bitmanip_a_reverse_ff.asSInt))
/////////////////////
val bitmanip_lzd_os = bitmanip_lzd_in
val bitmanip_dw_lzd_enc = WireInit(UInt(6.W),0.U)
bitmanip_dw_lzd_enc := MuxCase(0.U,(0 until 32).map(i=> (bitmanip_lzd_os(31,i)===0.U)->(32-i).U))//return leading zeros
val bitmanip_clz_ctz_result = Cat(Fill(6, ap_clz | ap_ctz) & bitmanip_dw_lzd_enc(5), Fill(5,!bitmanip_dw_lzd_enc(5)) & bitmanip_dw_lzd_enc(4,0) )
// * * * * * * * * * * * * * * * * * * BitManip : PCNT * * * * * * * * * * * * * * * * * *
val bitmanip_pcnt_result = Fill(6,ap_pcnt) & PopCount(io.a_in)
// * * * * * * * * * * * * * * * * * * BitManip : SEXT_B,SEXT_H * * * * * * * * * * * * * * * * *
val sel_shift = io.i0_ap.sll | io.i0_ap.srl | io.i0_ap.sra val bitmanip_sext_result = Mux1H(Seq(ap_sext_b -> Cat( Fill(24,io.a_in(7)) ,io.a_in(7,0)),
val sel_adder = (io.i0_ap.add | io.i0_ap.sub) & !io.i0_ap.slt ap_sext_h -> Cat( Fill(16,io.a_in(15)),io.a_in(15,0))) )
// * * * * * * * * * * * * * * * * * * BitManip : MIN,MAX,MINU,MAXU * * * * * * * * * * * * * * *
val bitmanip_minmax_sel = ap_min | ap_max;
val bitmanip_minmax_sel_a = ge ^ ap_min;
val bitmanip_minmax_result = Mux1H(Seq(
(bitmanip_minmax_sel & bitmanip_minmax_sel_a) -> io.a_in,
(bitmanip_minmax_sel & !bitmanip_minmax_sel_a) -> io.b_in.asSInt ))
// * * * * * * * * * * * * * * * * * * BitManip : PACK, PACKU, PACKH * * * * * * * * * * * * * * *
val bitmanip_pack_result = Fill(32,ap_pack) & Cat(io.b_in(15,0), io.a_in(15,0))
val bitmanip_packu_result = Fill(32,ap_packu) & Cat(io.b_in(31,16),io.a_in(31,16))
val bitmanip_packh_result = Fill(32,ap_packh) & Cat(0.U(16.W),io.b_in(7,0),io.a_in(7,0))
// * * * * * * * * * * * * * * * * * * BitManip : REV, REV8, ORC_B * * * * * * * * * * * * * * * *
val bitmanip_rev_result = Fill(32,ap_rev) & (0 until io.a_in.getWidth).map(i=> io.a_in(i).asUInt).reduce(Cat(_,_))
val bitmanip_rev8_result = Fill(32,ap_rev8) & (0 until io.a_in.getWidth/8).map(i=> io.a_in(7+i*8,0+i*8).asUInt).reduce(Cat(_,_)) //{a_in[7:0],a_in[15:8],a_in[23:16],a_in[31:24]};
// uint32_t gorc32(uint32_t rs1, uint32_t rs2)
// {
// uint32_t x = rs1;
// int shamt = rs2 & 31; ORC.B ORC16
// if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1); 1 0
// if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2); 1 0
// if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4); 1 0
// if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8); 0 0
// if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16); 0 1
// return x;
// }
// BEFORE 31 , 30 , 29 , 28 , 27 , 26, 25, 24
// shamt[0] b = a31|a30,a31|a30,a29|a28,a29|a28, a27|a26,a27|a26,a25|a24,a25|a24
// shamt[1] c = b31|b29,b30|b28,b31|b29,b30|b28, b27|b25,b26|b24,b27|b25,b26|b24
// shamt[2] d = c31|c27,c30|c26,c29|c25,c28|c24, c31|c27,c30|c26,c29|c25,c28|c24
//
// Expand d31 = c31 | c27;
// = b31 | b29 | b27 | b25;
// = a31|a30 | a29|a28 | a27|a26 | a25|a24
val bitmanip_orc_b_result = Fill(32,ap_orc_b) & (0 until io.a_in.getWidth/8).map(i=> Fill(8,io.a_in(7+i*8,0+i*8).orR).asUInt).reverse.reduce(Cat(_,_)) //{ {8{| a_in[31:24]}}, {8{| a_in[23:16]}}, {8{| a_in[15:8]}}, {8{| a_in[7:0]}} };
val bitmanip_orc16_result = Fill(32,ap_orc16) & Cat(io.a_in(31,16) | io.a_in(15,0), io.a_in(31,16) | io.a_in(15,0))
// * * * * * * * * * * * * * * * * * * BitManip : ZBSET, ZBCLR, ZBINV * * * * * * * * * * * * * *
val bitmanip_sb_1hot = "h00000001".U(32.W) << io.b_in(4,0)
val bitmanip_sb_data = Mux1H(Seq(
ap_sbset -> ( io.a_in | bitmanip_sb_1hot(31,0).asSInt),
ap_sbclr -> ( io.a_in & ~bitmanip_sb_1hot(31,0).asSInt),
ap_sbinv -> ( io.a_in ^ bitmanip_sb_1hot(31,0).asSInt) ))
val sel_shift = io.i0_ap.sll | io.i0_ap.srl | io.i0_ap.sra | ap_slo | ap_sro | ap_rol | ap_ror
val sel_adder = (io.i0_ap.add | io.i0_ap.sub | ap_zba) & !io.i0_ap.slt & !ap_min & !ap_max
val sel_pc = io.i0_ap.jal | io.pp_in.bits.pcall | io.pp_in.bits.pja | io.pp_in.bits.pret val sel_pc = io.i0_ap.jal | io.pp_in.bits.pcall | io.pp_in.bits.pja | io.pp_in.bits.pret
val csr_write_data = Mux(io.i0_ap.csr_imm.asBool, io.b_in.asSInt, io.a_in) val csr_write_data = Mux(io.i0_ap.csr_imm.asBool, io.b_in.asSInt, io.a_in)
@ -80,11 +301,29 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
// for jal or pcall, it will be the link address pc+2 or pc+4 // for jal or pcall, it will be the link address pc+2 or pc+4
val pcout = rvbradder(Cat(io.dec_i0_pc_d,0.U),Cat(io.dec_alu.dec_i0_br_immed_d,0.U)) val pcout = rvbradder(Cat(io.dec_i0_pc_d,0.U),Cat(io.dec_alu.dec_i0_br_immed_d,0.U))
result := lout(31,0) | Cat(0.U(31.W),slt_one) | (Mux1H(Seq( result := lout(31,0) | (Fill(32,sel_shift) & sout(31,0)) |
sel_shift.asBool -> sout(31,0), (Fill(32,sel_adder) & aout(31,0)) |
sel_adder.asBool -> aout(31,0), (Fill(32,sel_pc) & pcout ) |
sel_pc.asBool -> pcout, (Fill(32,io.i0_ap.csr_write) & csr_write_data(31,0)) |
io.i0_ap.csr_write.asBool -> csr_write_data(31,0)))) Cat(0.U(31.W), slt_one) |
(Fill(32,ap_sbext) & Cat(0.U(31.W), sout(0))) |
(Cat(0.U(26.W), bitmanip_clz_ctz_result(5,0))) |
(Cat(0.U(26.W), bitmanip_pcnt_result(5,0)) ) |
bitmanip_sext_result(31,0) |
bitmanip_minmax_result(31,0) |
bitmanip_pack_result(31,0) |
bitmanip_packu_result(31,0) |
bitmanip_packh_result(31,0) |
bitmanip_rev_result(31,0) |
bitmanip_rev8_result(31,0) |
bitmanip_orc_b_result(31,0) |
bitmanip_orc16_result(31,0) |
bitmanip_sb_data(31,0)
// lout(31,0) | Cat(0.U(31.W),slt_one) | (Mux1H(Seq(
// sel_shift.asBool -> sout(31,0),
// sel_adder.asBool -> aout(31,0),
// sel_pc.asBool -> pcout,
// io.i0_ap.csr_write.asBool -> csr_write_data(31,0))))
// *** branch handling *** // *** branch handling ***
@ -121,5 +360,3 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
io.predict_p_out.bits.ataken := actual_taken; // send a control signal telling it branch taken or not io.predict_p_out.bits.ataken := actual_taken; // send a control signal telling it branch taken or not
io.predict_p_out.bits.hist := newhist io.predict_p_out.bits.hist := newhist
} }

365
src/main/scala/exu/exu_mul_ctl.scala
View File

@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._ import chisel3.util._
import include._ import include._
import lib._ import lib._
import chisel3.stage.ChiselStage
class exu_mul_ctl extends Module with RequireAsyncReset with lib { class exu_mul_ctl extends Module with RequireAsyncReset with lib {
val io = IO(new Bundle{ val io = IO(new Bundle{
@ -22,7 +22,104 @@ class exu_mul_ctl extends Module with RequireAsyncReset with lib {
val prod_x = WireInit(SInt(66.W), 0.S) val prod_x = WireInit(SInt(66.W), 0.S)
val low_x = WireInit(0.U(1.W)) val low_x = WireInit(0.U(1.W))
// *** Start - BitManip ***
// val bitmanip_sel_d = WireInit(Bool(),0.B)
// val bitmanip_sel_x = WireInit(Bool(),0.B)
// val bitmanip_d = WireInit(UInt(32.W),0.U)
// val bitmanip_x = WireInit(UInt(32.W),0.U)
// ZBE
val ap_bext = WireInit(Bool(),0.B)
val ap_bdep = WireInit(Bool(),0.B)
// ZBC
val ap_clmul = WireInit(Bool(),0.B)
val ap_clmulh = WireInit(Bool(),0.B)
val ap_clmulr = WireInit(Bool(),0.B)
// ZBP
val ap_grev = WireInit(Bool(),0.B)
val ap_gorc = WireInit(Bool(),0.B)
val ap_shfl = WireInit(Bool(),0.B)
val ap_unshfl = WireInit(Bool(),0.B)
// ZBR
val ap_crc32_b = WireInit(Bool(),0.B)
val ap_crc32_h = WireInit(Bool(),0.B)
val ap_crc32_w = WireInit(Bool(),0.B)
val ap_crc32c_b = WireInit(Bool(),0.B)
val ap_crc32c_h = WireInit(Bool(),0.B)
val ap_crc32c_w = WireInit(Bool(),0.B)
// ZBF
val ap_bfp = WireInit(Bool(),0.B)
if (BITMANIP_ZBE == 1) {
ap_bext := io.mul_p.bits.bext
ap_bdep := io.mul_p.bits.bdep
}
else{
ap_bext := 0.U
ap_bdep := 0.U
}
if (BITMANIP_ZBC == 1) {
ap_clmul := io.mul_p.bits.clmul
ap_clmulh := io.mul_p.bits.clmulh
ap_clmulr := io.mul_p.bits.clmulr
}
else{
ap_clmul := 0.U
ap_clmulh := 0.U
ap_clmulr := 0.U
}
if (BITMANIP_ZBP == 1) {
ap_grev := io.mul_p.bits.grev
ap_gorc := io.mul_p.bits.gorc
ap_shfl := io.mul_p.bits.shfl
ap_unshfl := io.mul_p.bits.unshfl
}
else{
ap_grev := 0.U
ap_gorc := 0.U
ap_shfl := 0.U
ap_unshfl := 0.U
}
if (BITMANIP_ZBR == 1) {
ap_crc32_b := io.mul_p.bits.crc32_b
ap_crc32_h := io.mul_p.bits.crc32_h
ap_crc32_w := io.mul_p.bits.crc32_w
ap_crc32c_b := io.mul_p.bits.crc32c_b
ap_crc32c_h := io.mul_p.bits.crc32c_h
ap_crc32c_w := io.mul_p.bits.crc32c_w
}
else{
ap_crc32_b := 0.U
ap_crc32_h := 0.U
ap_crc32_w := 0.U
ap_crc32c_b := 0.U
ap_crc32c_h := 0.U
ap_crc32c_w := 0.U
}
if (BITMANIP_ZBF == 1) {
ap_bfp := io.mul_p.bits.bfp
}
else{
ap_bfp := 0.U
}
// *** End - BitManip ***
val mul_x_enable = io.mul_p.valid val mul_x_enable = io.mul_p.valid
val bit_x_enable = io.mul_p.valid
rs1_ext_in := Cat(io.mul_p.bits.rs1_sign & io.rs1_in(31),io.rs1_in).asSInt rs1_ext_in := Cat(io.mul_p.bits.rs1_sign & io.rs1_in(31),io.rs1_in).asSInt
rs2_ext_in := Cat(io.mul_p.bits.rs2_sign & io.rs2_in(31),io.rs2_in).asSInt rs2_ext_in := Cat(io.mul_p.bits.rs2_sign & io.rs2_in(31),io.rs2_in).asSInt
@ -31,5 +128,269 @@ class exu_mul_ctl extends Module with RequireAsyncReset with lib {
rs2_x := rvdffe (rs2_ext_in, mul_x_enable.asBool,clock,io.scan_mode) rs2_x := rvdffe (rs2_ext_in, mul_x_enable.asBool,clock,io.scan_mode)
prod_x := rs1_x * rs2_x prod_x := rs1_x * rs2_x
io.result_x := Mux1H (Seq(!low_x.asBool -> prod_x(63,32), low_x.asBool -> prod_x(31,0)))
// * * * * * * * * * * * * * * * * * * BitManip : BEXT, BDEP * * * * * * * * * * * * * * * * * *
// *** BEXT == "gather" ***
def one_cal (ind:Int) : UInt = if (ind == 0) io.rs2_in(ind) else (0 to ind).map(io.rs2_in(_).asUInt).reduce(_+&_)
val bext_d = (0 until 32).map(i=> MuxCase(false.B, (0 until 32).map(j=> (one_cal(j) === (i+1).U).asBool -> io.rs1_in(j).asUInt))).reverse.reduce(Cat(_,_))
// *** BDEP == "scatter" ***
val bdep_d =(0 until 32).map(j => Mux((io.rs2_in(j) === 1.U), io.rs1_in(one_cal(j)-1.U),0.U)).reverse.reduce(Cat(_,_))
// * * * * * * * * * * * * * * * * * * BitManip : CLMUL, CLMULH, CLMULR * * * * * * * * * * * * *
val clmul_raw_d = WireInit(UInt(63.W),0.U)
clmul_raw_d := (1 until 31).map(i => Fill(63,io.rs2_in(i)) & Cat(Fill(31-i,0.U),io.rs1_in(31,0),Fill(i,0.U))).reduce(_^_) ^ ( Fill(63,io.rs2_in(0)) & Cat(Fill(31,0.U),io.rs1_in) ) ^ ( Fill(63,io.rs2_in(31)) & Cat(io.rs1_in,Fill(31,0.U)) )
// * * * * * * * * * * * * * * * * * * BitManip : GREV * * * * * * * * * * * * * * * * * *
// uint32_t grev32(uint32_t rs1, uint32_t rs2)
// {
// uint32_t x = rs1;
// int shamt = rs2 & 31;
//
// if (shamt & 1) x = ( (x & 0x55555555) << 1) | ( (x & 0xAAAAAAAA) >> 1);
// if (shamt & 2) x = ( (x & 0x33333333) << 2) | ( (x & 0xCCCCCCCC) >> 2);
// if (shamt & 4) x = ( (x & 0x0F0F0F0F) << 4) | ( (x & 0xF0F0F0F0) >> 4);
// if (shamt & 8) x = ( (x & 0x00FF00FF) << 8) | ( (x & 0xFF00FF00) >> 8);
// if (shamt & 16) x = ( (x & 0x0000FFFF) << 16) | ( (x & 0xFFFF0000) >> 16);
//
// return x;
// }
val grev1_d = Mux(io.rs2_in(0), Range(0, 31, 2).map(i=> Cat(io.rs1_in(i),io.rs1_in(i+1))).reverse.reduce(Cat(_,_)), io.rs1_in)
val grev2_d = Mux(io.rs2_in(1), Range(0, 31, 4).map(i=> Cat(grev1_d(i+1,i),grev1_d(i+1+2,i+2))).reverse.reduce(Cat(_,_)) , grev1_d(31,0))
val grev4_d = Mux(io.rs2_in(2), Range(0, 31, 8).map(i=> Cat(grev2_d(i+3,i),grev2_d(i+3+4,i+4))).reverse.reduce(Cat(_,_)) , grev2_d(31,0))
val grev8_d = Mux(io.rs2_in(3), Range(0, 31, 16).map(i=> Cat(grev4_d(i+7,i),grev4_d(i+7+8,i+8))).reverse.reduce(Cat(_,_)), grev4_d(31,0))
val grev_d = Mux(io.rs2_in(4), Cat(grev8_d(15,0),grev8_d(31,16)), grev8_d(31,0) )
// * * * * * * * * * * * * * * * * * * BitManip : GORC * * * * * * * * * * * * * * * * * *
// uint32_t gorc32(uint32_t rs1, uint32_t rs2)
// {
// uint32_t x = rs1;
// int shamt = rs2 & 31;
//
// if (shamt & 1) x |= ( (x & 0x55555555) << 1) | ( (x & 0xAAAAAAAA) >> 1);
// if (shamt & 2) x |= ( (x & 0x33333333) << 2) | ( (x & 0xCCCCCCCC) >> 2);
// if (shamt & 4) x |= ( (x & 0x0F0F0F0F) << 4) | ( (x & 0xF0F0F0F0) >> 4);
// if (shamt & 8) x |= ( (x & 0x00FF00FF) << 8) | ( (x & 0xFF00FF00) >> 8);
// if (shamt & 16) x |= ( (x & 0x0000FFFF) << 16) | ( (x & 0xFFFF0000) >> 16);
//
// return x;
// }
// logic [31:0] gorc1_d;
// logic [31:0] gorc2_d;
// logic [31:0] gorc4_d;
// logic [31:0] gorc8_d;
// logic [31:0] gorc_d;
//
val gorc1_d = ( Fill(32,io.rs2_in(0)) & Range(0, 31, 2).map(i=> Cat(io.rs1_in(i),io.rs1_in(i+1))).reverse.reduce(Cat(_,_)) ) | io.rs1_in
val gorc2_d = ( Fill(32,io.rs2_in(1)) & Range(0, 31, 4).map(i=> Cat(gorc1_d(i+1,i),gorc1_d(i+1+2,i+2))).reverse.reduce(Cat(_,_)) ) | gorc1_d
val gorc4_d = ( Fill(32,io.rs2_in(2)) & Range(0, 31, 8).map(i=> Cat(gorc2_d(i+3,i),gorc2_d(i+3+4,i+4))).reverse.reduce(Cat(_,_)) ) | gorc2_d
val gorc8_d = ( Fill(32,io.rs2_in(3)) & Range(0, 31, 16).map(i=> Cat(gorc4_d(i+7,i),gorc4_d(i+7+8,i+8))).reverse.reduce(Cat(_,_)) ) | gorc4_d
val gorc_d = ( Fill(32,io.rs2_in(4)) & Cat(gorc8_d(15,0),gorc8_d(31,16)) ) | gorc8_d
// * * * * * * * * * * * * * * * * * * BitManip : SHFL, UNSHLF * * * * * * * * * * * * * * * * * *
// uint32_t shuffle32_stage (uint32_t src, uint32_t maskL, uint32_t maskR, int N)
// {
// uint32_t x = src & ~(maskL | maskR);
// x |= ((src << N) & maskL) | ((src >> N) & maskR);
// return x;
// }
//
//
//
// uint32_t shfl32(uint32_t rs1, uint32_t rs2)
// {
// uint32_t x = rs1;
// int shamt = rs2 & 15
//
// if (shamt & 8) x = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
// if (shamt & 4) x = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
// if (shamt & 2) x = shuffle32_stage(x, 0x30303030, 0xc0c0c0c0, 2);
// if (shamt & 1) x = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
//
// return x;
// }
val shfl8_d = Mux(io.rs2_in(3),Range(0, 9,8).map(i=> Cat(io.rs1_in(i+7+16,i+16),io.rs1_in(i+7,i))).reverse.reduce(Cat(_,_)) ,io.rs1_in)
val shfl4_d = Mux(io.rs2_in(2),Range(0, 13,4).map(i=> if(i<8) Cat(shfl8_d(i+3+8,i+8),shfl8_d(i+3,i))else Cat(shfl8_d(i+3+8+8,i+8+8),shfl8_d(i+3+8,i+8))).reverse.reduce(Cat(_,_)), shfl8_d)
val shfl2_d = Mux(io.rs2_in(1), Range(0, 15,2).map(i=> if(i<4)Cat(shfl4_d(i+1+4,i+4),shfl4_d(i+1,i))else if(i<8)Cat(shfl4_d(i+9,i+8),shfl4_d(i+5,i+4))else if(i<12)Cat(shfl4_d(i+13,i+12),shfl4_d(i+9,i+8))else Cat(shfl4_d(i+17,i+16),shfl4_d(i+13,i+12))).reverse.reduce(Cat(_,_)), shfl4_d)
val shfl_d = Mux(io.rs2_in(0), Range(0, 16,1).map(i=> if(i<2) Cat(shfl2_d(i+2),shfl2_d(i))else if(i<4) Cat(shfl2_d(i+4),shfl2_d(i+2))else if(i<6) Cat(shfl2_d(i+6),shfl2_d(i+4))else if(i<8) Cat(shfl2_d(i+8),shfl2_d(i+6))else if(i<10) Cat(shfl2_d(i+10),shfl2_d(i+8))else if(i<12) Cat(shfl2_d(i+12),shfl2_d(i+10))else if(i<14) Cat(shfl2_d(i+14),shfl2_d(i+12))else Cat(shfl2_d(i+16),shfl2_d(i+14))).reverse.reduce(Cat(_,_)), shfl2_d)
// // uint32_t unshfl32(uint32_t rs1, uint32_t rs2)
// // {
// // uint32_t x = rs1;
// // int shamt = rs2 & 15
// //
// // if (shamt & 1) x = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
// // if (shamt & 2) x = shuffle32_stage(x, 0x30303030, 0xc0c0c0c0, 2);
// // if (shamt & 4) x = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
// // if (shamt & 8) x = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
// //
// // return x;
// // }
//
//
val unshfl1_d = Mux(io.rs2_in(0) , Range(0, 16,1).map(i=> if(i<2) Cat(io.rs1_in(i+2),io.rs1_in(i))else if(i<4) Cat(io.rs1_in(i+4),io.rs1_in(i+2))else if(i<6) Cat(io.rs1_in(i+6),io.rs1_in(i+4))else if(i<8) Cat(io.rs1_in(i+8),io.rs1_in(i+6))else if(i<10) Cat(io.rs1_in(i+10),io.rs1_in(i+8))else if(i<12) Cat(io.rs1_in(i+12),io.rs1_in(i+10))else if(i<14) Cat(io.rs1_in(i+14),io.rs1_in(i+12))else Cat(io.rs1_in(i+16),io.rs1_in(i+14))).reverse.reduce(Cat(_,_)) , io.rs1_in)
val unshfl2_d =Mux(io.rs2_in(1) , Range(0, 15,2).map(i=> if(i<4)Cat(unshfl1_d(i+1+4,i+4),unshfl1_d(i+1,i))else if(i<8)Cat(unshfl1_d(i+9,i+8),unshfl1_d(i+5,i+4))else if(i<12)Cat(unshfl1_d(i+13,i+12),unshfl1_d(i+9,i+8))else Cat(unshfl1_d(i+17,i+16),unshfl1_d(i+13,i+12))).reverse.reduce(Cat(_,_)) , unshfl1_d)
val unshfl4_d = Mux(io.rs2_in(2) , Range(0, 13,4).map(i=> if(i<8) Cat(unshfl2_d(i+3+8,i+8),unshfl2_d(i+3,i))else Cat(unshfl2_d(i+3+8+8,i+8+8),unshfl2_d(i+3+8,i+8))).reverse.reduce(Cat(_,_)) , unshfl2_d)
val unshfl_d = Mux(io.rs2_in(3) , Range(0, 9,8).map(i=> Cat(unshfl4_d(i+7+16,i+16),unshfl4_d(i+7,i))).reverse.reduce(Cat(_,_)) , unshfl4_d)
// * * * * * * * * * * * * * * * * * * BitManip : BFP * * * * * * * * * * * * * * * * * *
val bfp_len = Cat(io.rs2_in(27,24) === 0.U,io.rs2_in(27,24)) // If LEN field is zero, then LEN=16
val bfp_off = io.rs2_in(20,16)
val bfp_len_mask_ = "hffff_ffff".U(32.W) << bfp_len
val bfp_preshift_data = io.rs2_in(15,0) & ~bfp_len_mask_(15,0)
val bfp_shift_data = Cat(Fill(16,0.U),bfp_preshift_data(15,0), Fill(16,0.U),bfp_preshift_data(15,0)) << bfp_off
val bfp_shift_mask = Cat(bfp_len_mask_(31,0), bfp_len_mask_(31,0)) << bfp_off
val bfp_result_d = bfp_shift_data(63,32) | (io.rs1_in & bfp_shift_mask(63,32))
// * * * * * * * * * * * * * * * * * * BitManip : CRC32, CRC32c * * * * * * * * * * * * * * * * *
// *** computed from https: //crccalc.com ***
//
// "a" is 8'h61 = 8'b0110_0001 (8'h61 ^ 8'hff = 8'h9e)
//
// Input must first be XORed with 32'hffff_ffff
//
//
// CRC32
//
// Input Output Input Output
// ----- -------- -------- --------
// "a" e8b7be43 ffffff9e 174841bc
// "aa" 078a19d7 ffff9e9e f875e628
// "aaaa" ad98e545 9e9e9e9e 5267a1ba
//
//
//
// CRC32c
//
// Input Output Input Output
// ----- -------- -------- --------
// "a" c1d04330 ffffff9e 3e2fbccf
// "aa" f1f2dac2 ffff9e9e 0e0d253d
// "aaaa" 6a52eeb0 9e9e9e9e 95ad114f
val crc32_all = ap_crc32_b | ap_crc32_h | ap_crc32_w | ap_crc32c_b | ap_crc32c_h | ap_crc32c_w
val crc32_poly_rev = "hEDB88320".U(32.W) // bit reverse of 32'h04C11DB7
val crc32c_poly_rev = "h82F63B78".U(32.W) // bit reverse of 32'h1EDC6F41
val crc32_bd = Wire(Vec(9,UInt(32.W)))
crc32_bd(0) := io.rs1_in
for(i <- 1 to 8) {
crc32_bd(i) := (crc32_bd(i-1) >> 1) ^ (crc32_poly_rev & Fill(32,crc32_bd(i-1)(0)))//io.rs1_in
}
val crc32_hd = Wire(Vec(17,UInt(32.W)))
crc32_hd(0) := io.rs1_in
for(i <- 1 to 16) {
crc32_hd(i) := (crc32_hd(i-1) >> 1) ^ (crc32_poly_rev & Fill(32,crc32_hd(i-1)(0)))//io.rs1_in
}
val crc32_wd = Wire(Vec(33,UInt(32.W)))
crc32_wd(0) := io.rs1_in
for(i <- 1 to 32) {
crc32_wd(i) := (crc32_wd(i-1) >> 1) ^ (crc32_poly_rev & Fill(32,crc32_wd(i-1)(0)))//io.rs1_in
}
/////////////////////////////////////////////////////////////////////////////////////////
val crc32c_bd = Wire(Vec(9,UInt(32.W)))
crc32c_bd(0) := io.rs1_in
for(i <- 1 to 8) {
crc32c_bd(i) := (crc32c_bd(i-1) >> 1) ^ (crc32c_poly_rev & Fill(32,crc32c_bd(i-1)(0)))//io.rs1_in
}
val crc32c_hd = Wire(Vec(17,UInt(32.W)))
crc32c_hd(0) := io.rs1_in
for(i <- 1 to 16) {
crc32c_hd(i) := (crc32c_hd(i-1) >> 1) ^ (crc32c_poly_rev & Fill(32,crc32c_hd(i-1)(0)))//io.rs1_in
}
val crc32c_wd = Wire(Vec(33,UInt(32.W)))
crc32c_wd(0) := io.rs1_in
for(i <- 1 to 32) {
crc32c_wd(i) := (crc32c_wd(i-1) >> 1) ^ (crc32c_poly_rev & Fill(32,crc32c_wd(i-1)(0)))//io.rs1_in
}
// * * * * * * * * * * * * * * * * * * BitManip : Common logic * * * * * * * * * * * * * * * * * *
val bitmanip_sel_d = ap_bext | ap_bdep | ap_clmul | ap_clmulh | ap_clmulr | ap_grev | ap_gorc | ap_shfl | ap_unshfl | crc32_all | ap_bfp
val bitmanip_d = Mux1H(Seq(
ap_bext -> bext_d(31,0) ,
ap_bdep -> bdep_d(31,0) ,
ap_clmul -> clmul_raw_d(31,0) ,
ap_clmulh -> Cat(0.U(1.W),clmul_raw_d(62,32)) ,
ap_clmulr -> clmul_raw_d(62,31) ,
ap_grev -> grev_d(31,0) ,
ap_gorc -> gorc_d(31,0) ,
ap_shfl -> shfl_d(31,0) ,
ap_unshfl -> unshfl_d(31,0) ,
ap_crc32_b -> crc32_bd(8)(31,0) ,
ap_crc32_h -> crc32_hd(16)(31,0) ,
ap_crc32_w -> crc32_wd(32)(31,0) ,
ap_crc32c_b -> crc32c_bd(8)(31,0) ,
ap_crc32c_h -> crc32c_hd(16)(31,0) ,
ap_crc32c_w -> crc32c_wd(32)(31,0) ,
ap_bfp -> bfp_result_d(31,0) ))
//rvdffe #(33) i_bitmanip_ff (.*, .clk(clk), .din({bitmanip_sel_d,bitmanip_d[31:0]}), .dout({bitmanip_sel_x,bitmanip_x[31:0]}), .en(bit_x_enable));
val bitmanip_sel_x = rvdffe(bitmanip_sel_d,bit_x_enable,clock,io.scan_mode)
val bitmanip_x = rvdffe(bitmanip_d,bit_x_enable,clock,io.scan_mode)
io.result_x := (Fill(32,~bitmanip_sel_x & ~low_x) & prod_x(63,32) ) |
(Fill(32,~bitmanip_sel_x & low_x) & prod_x(31,0) ) |
bitmanip_x
} }
object mul extends App {
println((new ChiselStage).emitVerilog(new exu_mul_ctl))}

90
src/main/scala/include/bundle.scala
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@ -175,6 +175,9 @@ class dma_dccm_ctl extends Bundle{
class lsu_exu extends Bundle{ class lsu_exu extends Bundle{
val exu_lsu_rs1_d = Input(UInt(32.W)) val exu_lsu_rs1_d = Input(UInt(32.W))
val exu_lsu_rs2_d = Input(UInt(32.W)) val exu_lsu_rs2_d = Input(UInt(32.W))
val lsu_result_m = Output(UInt(32.W))
val lsu_nonblock_load_data = Output(UInt(32.W))
} }
class lsu_dec extends Bundle { class lsu_dec extends Bundle {
val tlu_busbuff = new tlu_busbuff val tlu_busbuff = new tlu_busbuff
@ -323,6 +326,7 @@ class dbg_dctl extends Bundle{
class dec_alu extends Bundle { class dec_alu extends Bundle {
val dec_i0_alu_decode_d = Input(UInt(1.W)) // Valid val dec_i0_alu_decode_d = Input(UInt(1.W)) // Valid
val dec_csr_ren_d = Input(Bool()) // extra decode val dec_csr_ren_d = Input(Bool()) // extra decode
val dec_csr_rddata_d = Input(UInt(32.W))
val dec_i0_br_immed_d = Input(UInt(12.W)) // Branch offset val dec_i0_br_immed_d = Input(UInt(12.W)) // Branch offset
val exu_i0_pc_x = Output(UInt(31.W)) // flopped PC val exu_i0_pc_x = Output(UInt(31.W)) // flopped PC
} }
@ -364,13 +368,13 @@ class decode_exu extends Bundle with lib{
val i0_predict_index_d =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // DEC predict index val i0_predict_index_d =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // DEC predict index
val i0_predict_btag_d =Input(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag val i0_predict_btag_d =Input(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
val dec_i0_rs1_en_d =Input(UInt(1.W)) // Qualify GPR RS1 data val dec_i0_rs1_en_d =Input(UInt(1.W)) // Qualify GPR RS1 data
val dec_i0_branch_d =Input(UInt(1.W)) // Qualify GPR RS1 data
val dec_i0_rs2_en_d =Input(UInt(1.W)) // Qualify GPR RS2 data val dec_i0_rs2_en_d =Input(UInt(1.W)) // Qualify GPR RS2 data
val dec_i0_immed_d =Input(UInt(32.W)) // DEC data immediate val dec_i0_immed_d =Input(UInt(32.W)) // DEC data immediate
val dec_i0_rs1_bypass_data_d=Input(UInt(32.W)) // DEC bypass data val dec_i0_result_r =Input(UInt(32.W)) // DEC result in R-stage
val dec_i0_rs2_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
val dec_i0_select_pc_d =Input(UInt(1.W)) // PC select to RS1 val dec_i0_select_pc_d =Input(UInt(1.W)) // PC select to RS1
val dec_i0_rs1_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data val dec_i0_rs1_bypass_en_d =Input(UInt(4.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
val dec_i0_rs2_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data val dec_i0_rs2_bypass_en_d =Input(UInt(4.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
val mul_p =Flipped(Valid(new mul_pkt_t)) // DEC {valid, operand signs, low, operand bypass} val mul_p =Flipped(Valid(new mul_pkt_t)) // DEC {valid, operand signs, low, operand bypass}
val pred_correct_npc_x =Input(UInt(31.W)) // DEC NPC for correctly predicted branch val pred_correct_npc_x =Input(UInt(31.W)) // DEC NPC for correctly predicted branch
val dec_extint_stall =Input(Bool()) // External stall mux select val dec_extint_stall =Input(Bool()) // External stall mux select
@ -456,14 +460,12 @@ class predict_pkt_t extends Bundle {
val toffset = UInt(12.W) val toffset = UInt(12.W)
val br_error = UInt(1.W) val br_error = UInt(1.W)
val br_start_error = UInt(1.W) val br_start_error = UInt(1.W)
val prett = UInt(31.W)
val pcall = UInt(1.W) val pcall = UInt(1.W)
val pret = UInt(1.W)
val pja = UInt(1.W) val pja = UInt(1.W)
val way = UInt(1.W) val way = UInt(1.W)
val pret = UInt(1.W)
val prett = UInt(31.W)
} }
class trap_pkt_t extends Bundle { class trap_pkt_t extends Bundle {
val legal = UInt(1.W) val legal = UInt(1.W)
val icaf = UInt(1.W) val icaf = UInt(1.W)
@ -502,6 +504,31 @@ class reg_pkt_t extends Bundle {
class alu_pkt_t extends Bundle { class alu_pkt_t extends Bundle {
val clz = UInt(1.W)
val ctz = UInt(1.W)
val pcnt = UInt(1.W)
val sext_b = UInt(1.W)
val sext_h = UInt(1.W)
val slo = UInt(1.W)
val sro = UInt(1.W)
val min = UInt(1.W)
val max = UInt(1.W)
val pack = UInt(1.W)
val packu = UInt(1.W)
val packh = UInt(1.W)
val rol = UInt(1.W)
val ror = UInt(1.W)
val grev = UInt(1.W)
val gorc = UInt(1.W)
val zbb = UInt(1.W)
val sbset = UInt(1.W)
val sbclr = UInt(1.W)
val sbinv = UInt(1.W)
val sbext = UInt(1.W)
val sh1add = UInt(1.W)
val sh2add = UInt(1.W)
val sh3add = UInt(1.W)
val zba = UInt(1.W)
val land = UInt(1.W) val land = UInt(1.W)
val lor = UInt(1.W) val lor = UInt(1.W)
val lxor = UInt(1.W) val lxor = UInt(1.W)
@ -547,6 +574,51 @@ class lsu_error_pkt_t extends Bundle {
val addr = UInt(32.W) val addr = UInt(32.W)
} }
class dec_pkt_t extends Bundle { class dec_pkt_t extends Bundle {
val clz = Bool()
val ctz = Bool()
val pcnt = Bool()
val sext_b = Bool()
val sext_h = Bool()
val slo = Bool()
val sro = Bool()
val min = Bool()
val max = Bool()
val pack = Bool()
val packu = Bool()
val packh = Bool()
val rol = Bool()
val ror = Bool()
val grev = Bool()
val gorc = Bool()
val zbb = Bool()
val sbset = Bool()
val sbclr = Bool()
val sbinv = Bool()
val sbext = Bool()
val zbs = Bool()
val bext = Bool()
val bdep = Bool()
val zbe = Bool()
val clmul = Bool()
val clmulh = Bool()
val clmulr = Bool()
val zbc = Bool()
val shfl = Bool()
val unshfl = Bool()
val zbp = Bool()
val crc32_b = Bool()
val crc32_h = Bool()
val crc32_w = Bool()
val crc32c_b = Bool()
val crc32c_h = Bool()
val crc32c_w = Bool()
val zbr = Bool()
val bfp = Bool()
val zbf = Bool()
val sh1add = Bool()
val sh2add = Bool()
val sh3add = Bool()
val zba = Bool()
val alu = Bool() val alu = Bool()
val rs1 = Bool() val rs1 = Bool()
val rs2 = Bool() val rs2 = Bool()
@ -600,6 +672,7 @@ class dec_pkt_t extends Bundle {
} }
class mul_pkt_t extends Bundle { class mul_pkt_t extends Bundle {
// val valid = UInt(1.W)
val rs1_sign = UInt(1.W) val rs1_sign = UInt(1.W)
val rs2_sign = UInt(1.W) val rs2_sign = UInt(1.W)
val low = UInt(1.W) val low = UInt(1.W)
@ -609,6 +682,7 @@ class mul_pkt_t extends Bundle {
val clmulh = UInt(1.W) val clmulh = UInt(1.W)
val clmulr = UInt(1.W) val clmulr = UInt(1.W)
val grev = UInt(1.W) val grev = UInt(1.W)
val gorc = UInt(1.W)
val shfl = UInt(1.W) val shfl = UInt(1.W)
val unshfl = UInt(1.W) val unshfl = UInt(1.W)
val crc32_b = UInt(1.W) val crc32_b = UInt(1.W)

38
src/main/scala/lib/lib.scala
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@ -558,6 +558,44 @@ trait lib extends param{
} }
} }
} }
////////////////////////////////////////////////////////////////////////////////////////////////////
// special power flop for predict packet
// format: { LEFT, RIGHT==31 }
// LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
////////////////////////////////////////////////////////////////////////////////////////////////////////
def rvdffppe_UInt(din: UInt, clk: Clock, rst_l: AsyncReset, en : Bool, scan_mode: Bool, WIDTH: Int=32) = {
val RIGHT = 31
val LEFT = WIDTH - RIGHT
val LMSB = WIDTH-1
val LLSB = LMSB-LEFT+1
val RMSB = LLSB-1
val RLSB = LLSB-RIGHT
if(RV_FPGA_OPTIMIZE){
withClock(clk){
RegEnable(din,0.U.asTypeOf(din),en)
}
}else
Cat(rvdffe(din(LMSB,LLSB),en,clk,scan_mode),rvdffe(din(RMSB,RLSB),(en&din(LLSB)).asBool,clk,scan_mode))
}
object rvdffppe {
def apply(din: Bundle, clk: Clock, rst_l: AsyncReset, en : Bool, scan_mode: Bool, elements: Int,en_bit :Bool) = {
if(RV_FPGA_OPTIMIZE){
withClock(clk){
RegEnable(din,0.U.asTypeOf(din),en)
}
}
else{
val vec = MixedVecInit((0 until din.getElements.length).map(i=>
if(i<=elements) rvdffe(din.getElements(i).asUInt(),en,clk,scan_mode)
else rvdffe(din.getElements(i).asUInt(),(en& en_bit).asBool,clk,scan_mode)))
vec.asTypeOf(din)
}
}
}
//////////////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////////////
def rvdfflie_UInt(din: UInt, clk: Clock, rst_l: AsyncReset, en : Bool, scan_mode: Bool, WIDTH: Int=16, LEFT: Int=8) = { def rvdfflie_UInt(din: UInt, clk: Clock, rst_l: AsyncReset, en : Bool, scan_mode: Bool, WIDTH: Int=16, LEFT: Int=8) = {
val EXTRA = WIDTH-LEFT val EXTRA = WIDTH-LEFT

8
src/main/scala/lib/param.scala
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@ -161,4 +161,12 @@ trait param {
val BTB_ENABLE = 0x1 val BTB_ENABLE = 0x1
val BTB_TOFFSET_SIZE = 0x00C val BTB_TOFFSET_SIZE = 0x00C
val BTB_FULLYA = 0x00 val BTB_FULLYA = 0x00
val BITMANIP_ZBA = 0x00
val BITMANIP_ZBB = 0x01
val BITMANIP_ZBC = 0x00
val BITMANIP_ZBE = 0x00
val BITMANIP_ZBF = 0x00
val BITMANIP_ZBP = 0x00
val BITMANIP_ZBR = 0x00
val BITMANIP_ZBS = 0x01
} }

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