f7dbf106cc
trivial changes to increase performance
2021-01-15 09:09:52 +01:00
5b91897244
added likely, unlikely attributes to switch case, could boost perfomance
2020-06-21 00:22:51 +02:00
5ee634e4b4
Major refactoring!
...
* A_Instruction, C_Instruction and M_Instruction renamed to *_extension
* These files decode and executes extensions
* These classes use a new base clase extension_base
* Execute & Instruction classes heavyly modified:
* Execute now is BASE_ISA and decodes and executes base ISA, Zicsr & Zifencei
* Instruction keeps the instruction being executed, nothing else
* Add memory interface to ISS to clear the code and the structure
* Removed "using namespace " directives, all classes are called using their namespace
* Added proper header to each file
* Added license to all files
2020-06-02 13:08:38 +02:00
95b9685ad9
removed creation of class every CPU loop. It should get better performance
2020-05-28 17:18:50 +02:00
d575410a06
if condition clarified
2019-09-24 11:12:47 +02:00
5f0da6b208
fixed potential bug on memcpy
2019-09-24 11:02:15 +02:00
d63d95f634
fixed bug related DMI access when memory offset != 0
2019-09-10 12:24:46 +02:00
d42d67b991
DMI access added (if available)
2019-03-28 22:52:36 +01:00
a275e0fa24
better support to IRQs
2019-02-18 13:56:47 +01:00
2c93492ab1
enhanced IRQ support
2019-02-11 15:54:02 +01:00
098aebc15d
changed IRQ line to TLM socket
2019-01-22 12:43:05 +01:00
0c25abdb00
Fixed bug
2019-01-22 12:33:32 +01:00
a4a1be7386
IRQ implemented
2019-01-13 01:30:49 +01:00
a2a9c95546
Added A Extensions
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Added SFENCE instruction
2018-12-12 18:14:35 +01:00
1b93e7f569
added time management and cycle counters
2018-11-25 12:07:08 +01:00
c832b2f80f
all tests passed!
2018-11-22 16:42:06 +01:00
b9e26e4dea
first implementation supporting exceptions
2018-11-22 14:38:31 +01:00
ed7be704f9
implementation of all remaining C extension
2018-11-19 15:56:08 +01:00
3f7ecfa9df
bug fixes
2018-11-14 23:50:01 +01:00
a8bdc37c12
all tests passed!
2018-11-14 19:14:57 +01:00
d449ea5502
adding M extensions to simulator
2018-11-12 17:41:17 +01:00
bdf261cbc6
default value to variable to remove a warning
2018-11-12 17:08:26 +01:00
1fcbcf500b
typos 6 minor changes
2018-11-11 11:12:12 +01:00
97b15ca7a3
better (?) Log output
2018-10-15 17:34:42 +02:00
aa526943b9
Added instructions to pass riscv-tests
2018-10-15 13:51:41 +02:00
08044ac626
* Instruction: changed name to accessors
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* CPU: moved huge switch case to a new function
* Execute: changed to use instruction new accessors
2018-10-10 12:08:53 +02:00
a5773202e1
renamed RISC_V_execute to Execute
2018-09-21 13:05:42 +02:00
406d498209
added PC control
2018-09-21 09:24:25 +02:00
8dcbf09589
Lot of changes:
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* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
1c9bfe8c60
Added Data Memory bus. Implemented LW & SW instructions.
2018-09-17 12:21:26 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
mariusmonton